Parity-based Concurrent Error-detection Architecture Applied to the IDEA NXT Crypto-algorithm

  • Andreea Bozesan
  • Flavius Opritoiu
  • Mircea Vladutiu
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 356)


This paper presents a hardware architecture for online self-test in the context of the IDEA NXT crypto-algorithm. From the many techniques and solutions presented in the literature for increasing built-in self-test (BIST) capabilities, after a careful analysis of these approaches, we decided to focus our attention towards solutions based on parity-based error-detection. In this sense we designed and implemented a complete parity-based test architecture for IDEA NXT. The solution we propose doesn’t interfere in any way with the algorithm’s structure, as there is a complete separation between the functional and testing channels. The proposed solution is the first of this kind for the IDEA NXT crypto-algorithm. We evaluated the performance of the proposed test strategy with different redundancy levels and, formulated recommendations for the concurrent detection strategy based on the obtained experimental results.


Cryptography IDEA NXT Crypto-algorithm LFSR Concurrent-testing Parity-based verification 



This work was partially supported by the strategic grant POSDRU/159/1.5/S/137070 (2014) of the Ministry of National Education Protection, Romania, co-financed by the European Social Fund—Investing in People, within the Sectoral Operational Programme Human resources Development 2007–2013.


  1. 1.
    Junod P, Vaudenay S (2005) FOX specifications version 1.2, pp 5–40Google Scholar
  2. 2.
    Junod P, Vaudenay S (2005) Perfect diffusion primitives for block ciphers. In: Handschuh H, Hasan MA (eds) Selected areas in cryptography, lecture notes in computer science. Springer Berlin Heidelberg, pp 84–99Google Scholar
  3. 3.
    Opritoiu F, Vladutiu M, Udrescu M, Prodan L (2009) Round-level concurrent error detection applied to advanced encryption standard. Design and diagnostics of electronic circuits & systems, 2009. DDECS ‘09. In: 12th international symposium on, pp 270, 275Google Scholar
  4. 4.
    Chong Hee K, Quisquater JJ (2007) Faults, injection methods, and fault attacks. IEEE Design Test Comput 24(6):544–545Google Scholar
  5. 5.
    Bozesan A, Opritoiu F, Vladutiu M (2013) Hardware implementation of the IDEA NXT cryptoalgorithm. In: Design and technology in electronic packaging (SIITME), 2013 IEEE 19th international symposium for, pp 35, 38Google Scholar
  6. 6.
    Rao TRN, Fujiwara E (1989) Error-control coding for computer systems. Prentice-Hall InternationalGoogle Scholar
  7. 7.
    Daemen J, Rijmen V (2002) The design of Rijndael. Springer, New YorkGoogle Scholar
  8. 8.
    Courtois N, Pieprzyk J (2002) Cryptanalysis of block ciphers with over defined systems of equations. In: Advances in cryptology—ASIACRYPT’02, vol 2501 of lecture notes in computer science. Springer, pp 267–287Google Scholar
  9. 9.
    Avizienis A, Laprie J-C, Rendall B (2004) Basic concepts and taxonomy of dependable and secure computing. IEEE Trans Dependable Secure ComputGoogle Scholar
  10. 10.
    Security Requirements for Cryptographic Modules (2002) Federal information, processing standards publication 140–2Google Scholar
  11. 11.
    Burton Kaliski S Jr, Robshaw MJB (1994) Linear cryptanalysis using multiple approximationsGoogle Scholar
  12. 12.
    Meier W (1996) On the security of the IDEA block cipher. Adv CryptolGoogle Scholar
  13. 13.
    Coron JS, Goubin L (2000) On boolean and arithmetic masking against differential power analisys. In: Proceedings of workshop on cryptographic hardware and embedded systems—CHES 2000. Springer, pp 231–237Google Scholar
  14. 14.
    Moradi A, Mischke O, Paar C (2013) One attack to rule them all: collision timing attack versus 42 AES ASIC cores. IEEE Trans Comput 62(9):1786–1798MathSciNetCrossRefGoogle Scholar
  15. 15.
    Tarnick S (1994) Bounding error masking in linear output space compression schemes. Test symposium, 1994. In: Proceedings of the third Asian, pp 27, 32. Almukhaizim S, Makris Y (eds) Fault tolerant design of random logic based on a parity check code. Electrical Engineering Department Yale UniversityGoogle Scholar
  16. 16.
    Karpovsky M, Kulikowski KJ, Taubin A (2004) Differential fault analysis attack resistant architectures for the advanced encryption standard. Quisquater J-J, Paradinas P, Deswarte Y et al (eds) Smart card technologies and applications. Springer, pp 177–192Google Scholar
  17. 17.
    Cachin C, Camenisch J, Deswarte Y, Dobson J, Horne D, Kursawe K, Laprie, JC, Lebraud JC, Long D, McCucheon T, Muller J, Petzold F, Pfitzmann B, DGoogle Scholar
  18. 18.
    Daemon J, Govaerts R, Vandervale J (1994) Weak keys of IDEA. In: Advances in cryptology, CRYPTO 93 proceedings, lecture notes in computer science, vol 773. pp 224–231Google Scholar
  19. 19.
    Kitsos P, Sklavos N, Galanis MD, Koufopavlou O (2004) 64-bit block ciphers: hardware implementations and comparison analysis. In: VLSI Design Lab, Electr Comput Eng Dept 30(8). University of Patras, GreeceGoogle Scholar
  20. 20.
    Mozaffari-Kermani M, Reyhani-Masoleh A (2010) Concurrent structure-independent fault detection schemes for the advanced encryption standard. IEEE Trans Comput 59(5):608–622MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Andreea Bozesan
    • 1
  • Flavius Opritoiu
    • 1
  • Mircea Vladutiu
    • 1
  1. 1.University “Politehnica” of TimisoaraTimisoaraRomania

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