Rectangle Placement for VLSI Testing
We report our solution to the problem of designing test-site chips. This is a specific variation of the VLSI floorplanning problem where rectangular macros must be placed without overlap in a given area, but no wiring between the macros exists. Typically, industrial problems of this type require placing hundreds of macros of different sizes and shapes and include additional constraints such as fixing or grouping some of the macros. Many tools and techniques developed to solve similar problems proved unsuitable for this specific variation. We used constraint programming (CP) with additional heuristics, including sophisticated variable and value orderings, to produce floorplans for real test-sites. Our CP solution is successfully used in production by test-site designers.
KeywordsFloorplanning Electronic design automation Constraint programming Non overlapping rectangles placement
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- 2.Lauther, U.: A Min-cut placement algorithm for general cell assemblies based on a graph representation. In: Papers on Twenty-five Years of Electronic Design Automation, pp. 182–191. ACM, New York (1988)Google Scholar
- 3.Khatkhate, A., Li, C., Agnihotri, A.R., Yildiz, M.C., Ono, S., Koh, C.K., Madden, P.H.: Recursive bisection based mixed block placement. In: Procceedings of ACM International Symposium on Physical Design, pp. 84–89. ACM (2004)Google Scholar
- 4.Gerez, S.H.: Algorithms for VLSI Design Automation. John Wiley & Sons(2000)Google Scholar
- 5.Chang, Y.C., Chang, Y.W., Wu, G.M., Wu, S.W. : B*-trees: a new representation for non-slicing floorplans. In: Proccedings of the Design Automation Conference, pp 458–463 (2000)Google Scholar
- 6.Adya, S.N., Chaturvedi, S., Roy, J.A., Papa, D.A., Markov, I.L.: Unification of partitioning, placement and floorplanning. In: Proceedings of the 2004 IEEE/ACM International Conference on Computer-aided Design, pp. 550–557. IEEE Computer Society, Washington DC (2004)Google Scholar
- 7.Chan, T.F., Cong, J., Shinnerl, J.R., Sze, K., Xie, M.: mPL6: enhanced multilevel mixed-size placement. In: Proceedings of the 2006 International Symposium on Physical Design, pp. 212–214. ACM, New York (2006)Google Scholar
- 8.Chen, T.C., Hsu, T.C., Jiang, Z.W., Chang, Y.M.: NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. In: Proceedings of the 2005 International Symposium on Physical Design, pp. 236–238. ACM, New York (2005)Google Scholar
- 9.Batra, D.: Analysis of Floorplanning Algorithms in VLSI Physical Designs. International Journal of Advanced Technology & Engineering Research 2(5), 62–71 (2012)Google Scholar
- 11.IBM Research - Haifa CP solver. http://www.research.ibm.com/haifa/dept/vst/csp_gec.shtml