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A Hybrid Approach for Parallel Transistor-Level Full-Chip Circuit Simulation

  • Heidi K. Thornquist
  • Sivasankaran Rajamanickam
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8969)

Abstract

The computer-aided design (CAD) applications that are fundamental to the electronic design automation industry need to harness the available hardware resources to be able to perform full-chip simulation for modern technology nodes (45 nm and below). We will present a hybrid (MPI+threads) approach for parallel transistor-level transient circuit simulation that achieves scalable performance for some challenging large-scale integrated circuits. This approach focuses on the computationally expensive part of the simulator: the linear system solve. Hybrid versions of two iterative linear solver strategies are presented, one takes advantage of block triangular form structure while the other uses a Schur complement technique. Results indicate up to a 27x improvement in total simulation time on 256 cores.

Keywords

Linear Solver Total Simulation Time Electronic Design Automation Block Triangular Form Sparse Direct Solver 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  • Heidi K. Thornquist
    • 1
  • Sivasankaran Rajamanickam
    • 1
  1. 1.Sandia National LaboratoriesAlbuquerqueUSA

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