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Design of a Transparent Pipeline-Based Multiplier

  • Ren-Der Chen
  • Xiang-Chih Kuo
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 345)

Abstract

This chapter implements an 8 × 8 multiplier based on the transparent pipeline architecture. A transparent pipeline can lower the power consumption by reducing the number of clock pulses required for data latch controlling. The efficiency of power saving is evaluated here by applying the multiplier to the multiplication of two sparse matrices. It can be seen from the experimental results that, when compared with the traditional synchronous multiplier using flip-flops as storage elements, the improvement in power consumption is obvious only when the sparsity of the matrix reaches a certain amount.

Keywords

Transparent pipeline Multiplier Sparse matrix 

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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.Department of Computer Science and Information EngineeringNational Changhua University of EducationChanghuaTaiwan

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