Design of a Transparent Pipeline-Based Multiplier

  • Ren-Der Chen
  • Xiang-Chih Kuo
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 345)


This chapter implements an 8 × 8 multiplier based on the transparent pipeline architecture. A transparent pipeline can lower the power consumption by reducing the number of clock pulses required for data latch controlling. The efficiency of power saving is evaluated here by applying the multiplier to the multiplication of two sparse matrices. It can be seen from the experimental results that, when compared with the traditional synchronous multiplier using flip-flops as storage elements, the improvement in power consumption is obvious only when the sparsity of the matrix reaches a certain amount.


Transparent pipeline Multiplier Sparse matrix 


  1. 1.
    Benini, L., De Micheli, G.: Automatic synthesis of low-power gated-clock finite-state machines. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 15(6), 630–643 (1996)CrossRefGoogle Scholar
  2. 2.
    Choi, J.-H., Kim, B.-G., Dasgupta, A., Roy, K.: Improved clock-gating control scheme for transparent pipeline. In: 15th Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, pp. 401–406 (2010)Google Scholar
  3. 3.
    Hill, E.L., Lipasti, M.H.: Transparent mode flip-flops for collapsible pipelines. In: 25th International Conference on Computer Design (ICCD), Lake Tahoe, pp. 553–560 (2007)Google Scholar
  4. 4.
    Jacobson, H.M.: Improved clock-gating through transparent pipelining. In: International Symposium on Low Power Electronics and Design (ISLPED), Newport Beach, pp. 26–31 (2004)Google Scholar
  5. 5.
    Kuzmanov, G., Taouil, M.: Reconfigurable sparse/dense matrix-vector multiplier. In: International Conference on Field-Programmable Technology (FPT), Sydney, pp. 483–488 (2009)Google Scholar
  6. 6.
    Matam, K., Indarapu, S.R.K.B., Kothapalli, K.: Sparse matrix-matrix multiplication on modern architectures. In: 19th International Conference on High Performance Computing (HiPC), Hyderabad, pp. 1–10. (2012)Google Scholar
  7. 7.
    Wu, Q., Pedram, M., Wu, X.: Clock-gating and its application to low power design of sequential circuits. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 47(103), 415–420 (2000)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.Department of Computer Science and Information EngineeringNational Changhua University of EducationChanghuaTaiwan

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