A Study on the Performance Characteristics of a Synchronous Elastic FIR Filter

  • Ren-Der Chen
  • Sheng-Yu Kao
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 345)


Elastic systems provide tolerance to the unpredictable timing variations in computation and communication delays. For a synchronous elastic circuit, the handshaking mechanism to synchronize the data communication between sender and receiver is produced at the level of cycle in which the events are synchronized with the clock. In this chapter, the performance characteristics, i.e., area, delay, and power, of a synchronous elastic circuit are studied by the implementation of a finite impulse response (FIR) filter. The filter is designed as a two-stage pipeline, and to be compared with its non-elastic counterpart, both ASIC and FPGA implementations have been made for various orders of the filter.


Elastic FIR Filter 


  1. 1.
    Carmona, J., Cortadella, J., Kishinevsky, M., Taubin, A.: Elastic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst 28(10), 1437–1455 (2009)CrossRefGoogle Scholar
  2. 2.
    Casu, M.R.: Half-buffer retiming and token cages for synchronous elastic circuits. IET Comput. Digit. Tech. 5(4), 318–330 (2011)CrossRefGoogle Scholar
  3. 3.
    Cortadella, J., Galceran-Oms, M., Kishinevsky, M.: Elastic systems. In: 8th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE), Grenoble, pp. 149–158 (2010)Google Scholar
  4. 4.
    Chang, T.-S., Jen, C.-W.: Hardware-efficient pipelined programmable FIR filter design. IEE Comput. Digit. Tech. 148(6), 227–232 (2001)CrossRefGoogle Scholar
  5. 5.
    Deepak, G., Meher, P. K., Sluzek, A.: Performance characteristics of parallel and pipelined implementation of FIR filters in FPGA platform. In: International Symposium on Signals, Circuits and Systems (ISSCS), pp. 1–4 (2007)Google Scholar
  6. 6.
    Singh, M., Tierno, J.A., Rylyakov, A., Rylov, S., Nowick, S.M.: An adaptively pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 Gigahertz. IEEE Trans. VLSI Syst. 18(7), 1043–1056 (2010)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.Department of Computer Science and Information EngineeringNational Changhua University of EducationChanghuaTaiwan

Personalised recommendations