A Study on the Performance Characteristics of a Synchronous Elastic FIR Filter
Elastic systems provide tolerance to the unpredictable timing variations in computation and communication delays. For a synchronous elastic circuit, the handshaking mechanism to synchronize the data communication between sender and receiver is produced at the level of cycle in which the events are synchronized with the clock. In this chapter, the performance characteristics, i.e., area, delay, and power, of a synchronous elastic circuit are studied by the implementation of a finite impulse response (FIR) filter. The filter is designed as a two-stage pipeline, and to be compared with its non-elastic counterpart, both ASIC and FPGA implementations have been made for various orders of the filter.
KeywordsElastic FIR Filter
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