Abstract
The aim of this book was to develop circuit and architectural techniques to design ultra-low-voltage digital circuits with high energy-efficiency in CMOS technologies. Another essential target of this research has been to design circuits which are able to operate at frequencies of n × 10 MHz. Furthermore, it is found to be imperative to achieve a high variation-resilience of these circuits in order to guarantee a high yield. Techniques on how to achieve these goals have been demonstrated throughout the book. This chapter provides an extensive conclusion of this research. It includes an overview of the conclusions which were reached throughout the book. Moreover, the obtained results of the prototypes are situated in the current state-of-the-art in literature. This chapter also presents the main contributions of this research. Finally, this book concludes by a look at future perspectives for follow-up research.
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Reference
Reyserhove H, Reynders N, Dehaene W (2014) Ultra-low voltage datapath blocks in 28 nm UTBB FD-SOI. In: Proceedings of the IEEE Asian solid-state circuits conference (A-SSCC), pp 49–52. DOI: 10.1109/ASSCC.2014.7008857
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Reynders, N., Dehaene, W. (2015). Conclusion. In: Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-16136-5_7
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DOI: https://doi.org/10.1007/978-3-319-16136-5_7
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-16135-8
Online ISBN: 978-3-319-16136-5
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