- 1.4k Downloads
This chapter presents the design of the first three ultra-low-voltage prototypes which have been implemented in this book. These prototypes all consist of datapath blocks. Their target was to be able to operate at ultra-low supply voltages, while achieving high energy-efficiency, a speed of n × 10MHz and a high yield through variation-resilience. This chapter builds further upon the conclusions of the analyses of different gate-level building blocks and of architectural design choices. The chapter starts with a discussion on the design of the first prototype, which is a 32-bit logarithmic adder fabricated in a 90nm CMOS technology. This prototype is employed as a proof of concept to confirm the robust operation of Transmission Gate logic and latch-based deep pipelining in the ultra-low-voltage region. Extensive measurement results evaluate their successful functionality and are compared to the state-of-the-art. Furthermore, this chapter examines the ultra-low-voltage design of a 16-bit Multiply-Accumulate unit. This MAC has been fabricated in both the 90nm and the 40nm CMOS technologies at hand, resulting in the second and the third prototype. Gate-level and architectural improvements with respect to the design of the adder are implemented and tested. An extensive comparison between the measurement results of the MAC in both CMOS technologies allows studying the impact of scaling on ultra-low-voltage designs.
KeywordsDatapath Block Multiply-accumulate Unit 90-nm CMOS Technology Resilience Variables Architectural Design Choices
- 2.Bol D, Kamel D, Flandre D, Legat JD (2009) Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. In: Proceedings of the ACM/IEEE international symposium on low power electronics and design (ISLPED), pp 3–8. DOI:10.1145/1594233.1594237Google Scholar
- 8.Reynders N, Dehaene W (2011) A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques. In: Proceedings of the IEEE Asian solid-state circuits conference (A-SSCC), pp 113–116. DOI:10.1109/ASSCC.2011.6123617Google Scholar
- 9.Reynders N, Dehaene W (2012) Variation-resilient sub-threshold circuit solutions for ultra-low-power digital signal processors with 10MHz clock frequency. In: Proceedings of the IEEE European solid-state circuits conference (ESSCIRC), pp 474–477. DOI:10.1109/ESSCIRC. 2012.6341358Google Scholar