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This chapter explores various architectural options for the prototypes of this book. By examining their benefits and drawbacks, recommendations are provided for efficient and robust ultra-low-voltage functionality. This chapter starts with theoretical considerations on energy consumption, specifically for transistors operating in the weak inversion region and for circuits which are subjected to high variability. Next, the chapter explores architectural consequences of using Transmission Gate logic. A focus is given to the cascading of logic gates and how this can be implemented taking into account the need for complementary input signals, as well as the necessary regeneration of the voltage levels of the output signals. The advantages and disadvantages of increasing the logic depth are discussed. Furthermore, attention will be given to differential TG logic and its consequences. If the aforementioned regeneration is performed by clocked elements, pipelining is introduced. Various pipelining schemes are explored to assess their suitability for sub- or near-threshold designs. Several parameters have a large influence on pipelined architectures, resulting in design considerations which are often contradictory. To be able to provide recommendations for the field of interest and possible applications of this book, these considerations are therefore evaluated carefully. Furthermore, the design methodology which is based on the conclusions of both this and the previous chapter is presented. The different steps which are used to design and layout the prototypes of this book are discussed profoundly. Finally, this chapter discusses the I/O circuits required for the measurement setup of the prototypes.
KeywordsMaximum Logic Depth Weak Inversion Region Cascaded Logic Gates Transmission Gate Logic Borrowed Time
- 1.Harris D (2001) Skew-tolerant circuit design. Morgan Kaufmann, San FranciscoGoogle Scholar
- 4.Reynders N, Dehaene W (2012) Variation-resilient sub-threshold circuit solutions for ultra-low-power digital signal processors with 10 MHz clock frequency. In: Proceedings of the IEEE European solid-state circuits conference (ESSCIRC), pp 474–477. DOI: 10.1109/ESSCIRC.2012.6341358Google Scholar
- 5.Weiss O, Gansen M, Noll T (2001) A flexible datapath generator for physical oriented design. In: Proceedings of the IEEE European solid-state circuits conference (ESSCIRC), pp 393–396Google Scholar
- 6.Weste N, Harris D (2011) CMOS VLSI design: a circuits and systems perspective, 4th edn. Addison-Wesley, BostonGoogle Scholar