Advertisement

Gate-Level Building Blocks

  • Nele Reynders
  • Wim Dehaene
Chapter
  • 1.4k Downloads
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

This chapter discusses the gate-level building blocks which have been used to design the ultra-low-voltage prototypes of this work. Their aim was not only to operate at very low supply voltages in a variation-resilient manner, but also to function at speeds of n × 10 MHz. Such targets are only possible to achieve when attention is paid to both the transistor-level basic circuits and the architectural level. Careful design of logic gates is crucial if they should be able to efficiently work in the ultra-low-voltage region. Their topology not only has a large impact on the variation-resilience of the total design, but also on the delay, leakage power and active energy consumption. Therefore, this chapter provides an elaborate comparison of circuit topologies, from very common logic families to more exotic circuit topologies which have been specifically proposed for operation in the ultra-low-voltage region. An in-depth analysis of the characteristics of these logic families leads to the presentation of the circuit topologies that are preferred in this work. The chapter continues this discussion of basic building blocks by exploring various memory elements. Not only their functionality differences are examined, but the trade-offs that accompany operation at low supply voltages as well. To conclude, a summary of the different sizing options of the basic building blocks which have been employed in the four prototypes in this book is given.

Keywords

Resilience Variables Adiabatic Logic Standard CMOS Inverter Pass Transistor Logic Tristate Inverter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Akgun O, Rodrigues J, Leblebici Y, Owall V (2012) High-level energy estimation in the sub-Vt domain: simulation and measurement of a cardiac event detector. IEEE Tran Biomed Circuits Syst 6(1):15–27. DOI: 10.1109/TBCAS.2011.2157505CrossRefGoogle Scholar
  2. 2.
    Alarcón LP, Liu TT, Pierson MD, Rabaey JM (2007) Exploring very low-energy logic: a case study. J Low Power Electron 3(3):223–233. DOI: 10.1166/jolpe.2007.136CrossRefGoogle Scholar
  3. 3.
    Alioto M (2010) Understanding DC behavior of subthreshold CMOS logic through closed-form analysis. IEEE Trans Circuits Syst Regul Pap 57(7):1597–1607. DOI: 10.1109/TCSI.2009.2034233CrossRefMathSciNetGoogle Scholar
  4. 4.
    Alioto M (2012) Ultra-low power VLSI circuit design demystified and explained: a tutorial. IEEE Trans Circuits Syst Regul Pap 59(1):3–29. DOI: 10.1109/TCSI.2011.2177004CrossRefMathSciNetGoogle Scholar
  5. 5.
    Amirante E, Fischer J, Lang M, Bargagli-Stoffi A, Berthold J, Heer C, Schmitt-Landsiedel D (2003) An ultra low-power adiabatic adder embedded in a standard 0.13 μm CMOS environment. In: Proceedings of the IEEE European solid-state circuits conference (ESSCIRC), pp 599–602. DOI: 10.1109/ESSCIRC.2003.1257206Google Scholar
  6. 6.
    Bol D, Ambroise R, Flandre D, Legat JD (2009) Interests and limitations of technology scaling for subthreshold logic. IEEE Trans Very Large Scale Integr VLSI Syst 17(10):1508–1519. DOI: 10.1109/TVLSI.2008.2005413CrossRefGoogle Scholar
  7. 7.
    Bol D, De Vos J, Hocquet C, Botman F, Durvaux F, Boyd S, Flandre D, Legat JD (2013) Sleepwalker: A 25-MHz 0.4-V sub-mm2 7-μW/MHz microcontroller in 65-nm LP/GP CMOS for low-carbon wireless sensor nodes. IEEE J Solid State Circuits 48(1):20–32. DOI: 10.1109/JSSC.2012.2218067CrossRefGoogle Scholar
  8. 8.
    Calhoun B, Chandrakasan A (2006) Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering. IEEE J Solid State Circuits 41(1):238–245. DOI: 10.1109/JSSC.2005.859886CrossRefGoogle Scholar
  9. 9.
    Chang IJ, Park SP, Roy K (2010) Exploring asynchronous design techniques for process-tolerant and energy-efficient subthreshold operation. IEEE J Solid State Circuits 45(2):401–410. DOI: 10.1109/JSSC.2009.2036764CrossRefGoogle Scholar
  10. 10.
    Clerc S, Abouzeid F, Argoud F, Kumar A, Kumar R, Roche P (2011) A 240 mV 1 MHz, 340 mV 10 MHz, 40 nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform. In: Proceedings of the IEEE international conference on electronics, circuits and systems (ICECS), pp 117–120. DOI: 10.1109/ICECS.2011.6122228Google Scholar
  11. 11.
    Hanson S, Seok M, Sylvester D, Blaauw D (2008) Nanometer device scaling in subthreshold logic and SRAM. IEEE Trans Electron Devices 55(1):175–185. DOI: 10.1109/TED.2007.911033CrossRefGoogle Scholar
  12. 12.
    Hanson S, Zhai B, Seok M, Cline B, Zhou K, Singhal M, Minuth M, Olson J, Nazhandali L, Austin T, Sylvester D, Blaauw D (2008) Exploring variability and performance in a sub-200-mV processor. IEEE J Solid State Circuits 43(4):881–891. DOI: 10.1109/JSSC.2008.917505CrossRefGoogle Scholar
  13. 13.
    Henzler S (2007) Power management of digital circuits in deep sub-micron CMOS technologies. Springer, New YorkGoogle Scholar
  14. 14.
    Hwang ME, Raychowdhury A, Kim K, Roy K (2007) A 85 mV 40 nW process-tolerant subthreshold 8x8 FIR filter in 130nm technology. In: Proceedings of the IEEE symposium on VLSI circuits (VLSIC), pp 154–155. DOI: 10.1109/VLSIC.2007.4342695Google Scholar
  15. 15.
    Jain S, Khare S, Yada S, Ambili V, Salihundam P, Ramani S, Muthukumar S, Srinivasan M, Kumar A, Gb S, Ramanarayanan R, Erraguntla V, Howard J, Vangal S, Dighe S, Ruhl G, Aseron P, Wilson H, Borkar N, De V, Borkar S (2012) A 280 mV-to-1.2 V wide-operating-range IA-32 processor in 32 nm CMOS. In: Proceedings of the IEEE international solid-state circuits conference (ISSCC), pp 66–68. DOI: 10.1109/ISSCC.2012.6176932Google Scholar
  16. 16.
    Jeon D, Seok M, Chakrabarti C, Blaauw D, Sylvester D (2012) A super-pipelined energy efficient subthreshold 240 MS/s FFT core in 65 nm CMOS. IEEE J Solid State Circuits 47(1):23–34. DOI: 10.1109/JSSC.2011.2169311CrossRefGoogle Scholar
  17. 17.
    Jocke SC, Bolus J, Wooters S, Jurik A, Weaver A, Blalock T, Calhoun B (2009) A 2.6-μW sub-threshold mixed-signal ECG SoC. In: Proceedings of the IEEE symposium on VLSI circuits (VLSIC), pp 60–61Google Scholar
  18. 18.
    Kao J, Miyazaki M, Chandrakasan A (2002) A 175-mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture. IEEE J Solid State Circuits 37(11):1545–1554. DOI: 10.1109/JSSC.2002.803957CrossRefGoogle Scholar
  19. 19.
    Kaul H, Anders M, Mathew S, Hsu S, Agarwal A, Krishnamurthy R, Borkar S (2008) A 320 mV 56 μW 411GOPS/Watt ultra-low voltage motion estimation accelerator in 65nm CMOS. In: Proceedings of the IEEE international solid-state circuits conference (ISSCC), pp 316–317. DOI: 10.1109/ISSCC.2008.4523184Google Scholar
  20. 20.
    Klinefelter A, Zhang Y, Otis B, Calhoun B (2012) A programmable 34 nW/channel sub-threshold signal band power extractor on a body sensor node SoC. IEEE Trans Circuits Syst Express Briefs 59(12):937–941. DOI: 10.1109/TCSII.2012.2231041CrossRefGoogle Scholar
  21. 21.
    Konijnenburg M, Cho Y, Ashouei M, Gemmeke T, Kim C, Hulzink J, Stuyt J, Jung M, Huisken J, Ryu S, Kim J, de Groot H (2013) Reliable and energy-efficient 1 MHz 0.4 V dynamically reconfigurable SoC for ExG applications in 40 nm LP CMOS. In: Proceedings of the IEEE international solid-state circuits conference (ISSCC), pp 430–431. DOI: 10.1109/ISSCC.2013.6487801Google Scholar
  22. 22.
    Kwong J, Chandrakasan A (2006) Variation-driven device sizing for minimum energy sub-threshold circuits. In: Proceedings of the ACM/IEEE international symposium on low power electronics and design (ISLPED), pp 8–13. DOI: 10.1109/LPE.2006.4271799Google Scholar
  23. 23.
    Kwong J, Ramadass Y, Verma N, Chandrakasan A (2009) A 65 nm sub-Vt microcontroller with integrated SRAM and switched capacitor DC-DC converter. IEEE J Solid State Circuits 44(1):115–126. DOI: 10.1109/JSSC.2008.2007160CrossRefGoogle Scholar
  24. 24.
    Lutkemeier S, Jungeblut T, Berge H, Aunet S, Porrmann M, Ruckert U (2013) A 65 nm 32b subthreshold processor with 9T multi-Vt SRAM and adaptive supply voltage control. IEEE J Solid State Circuits 48(1):8–19. DOI: 10.1109/JSSC.2012.2220671CrossRefGoogle Scholar
  25. 25.
    Makipää J, Turnquist MJ, Laulainen E, Koskinen L (2012) Timing-error detection design considerations in subthreshold: an 8-bit microprocessor in 65 nm CMOS. J Low Power Electron Appl 2(2):180–196. DOI: 10.3390/jlpea2020180CrossRefGoogle Scholar
  26. 26.
    Narendra S, Borkar S, De V, Antoniadis D, Chandrakasan A (2001) Scaling of stack effect and its application for leakage reduction. In: Proceedings of the ACM/IEEE international symposium on low power electronics and design (ISLPED), pp 195–200. DOI: 10.1109/LPE.2001.945400Google Scholar
  27. 27.
    Narendra S, Keshavarzi A, Bloechel B, Borkar S, De V (2003) Forward body bias for microprocessors in 130-nm technology generation and beyond. IEEE J Solid-State Circuits 38(5):696–701. DOI: 10.1109/JSSC.2003.810054CrossRefGoogle Scholar
  28. 28.
    Narendra S, Chandrakasan A (2006) Leakage in nanometer CMOS technologies. Springer, BerlinGoogle Scholar
  29. 29.
    Pu Y, Pineda de Gyvez J, Corporaal H, Ha Y (2007) Vt balancing and device sizing towards high yield of sub-threshold static logic gates. In: Proceedings of the ACM/IEEE international symposium on low power electronics and design (ISLPED), pp 355–358. DOI: 10.1145/1283780.1283857Google Scholar
  30. 30.
    Pu Y, Pineda de Gyvez J, Corporaal H, Ha Y (2010) An ultra-low-energy multi-standard JPEG co-processor in 65 nm CMOS with sub/near threshold supply voltage. IEEE J Solid State Circuits 45(3):668–680. DOI: 10.1109/JSSC.2009.2039684CrossRefGoogle Scholar
  31. 31.
    Rabaey J, Chandrakasan A, Nikolic B (2003) Digital integrated circuits: a design perspective, 2nd edn. Prentice Hall, Englewood CliffsGoogle Scholar
  32. 32.
    Reynders N, Dehaene W (2011) A 190 mV supply, 10 MHz, 90 nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques. In: Proceedings of the IEEE Asian solid-state circuits conference (A-SSCC), pp 113–116. DOI: 10.1109/ASSCC.2011.6123617Google Scholar
  33. 33.
    Reynders N, Dehaene W (2012) Variation-resilient building blocks for ultra-low-energy sub-threshold design. IEEE Trans Circuits Syst Express Briefs 59(12):898–902. DOI: 10.1109/TCSII.2012.2231022CrossRefGoogle Scholar
  34. 34.
    Reynders N, Dehaene W (2012) Variation-resilient sub-threshold circuit solutions for ultra-low-power digital signal processors with 10 MHz clock frequency. In: Proceedings of the IEEE European solid-state circuits conference (ESSCIRC), pp 474–477. DOI: 10.1109/ESSCIRC.2012.6341358Google Scholar
  35. 35.
    Soeleman H, Roy K (1999) Ultra-low power digital subthreshold logic circuits. In: Proceedings of the ACM/IEEE international symposium on low power electronics and design (ISLPED), pp 94–96Google Scholar
  36. 36.
    Soeleman H, Roy K, Paul B (2001) Sub-domino logic: ultra-low power dynamic sub-threshold digital logic. In: Proceedings of the IEEE international conference on VLSI design, pp 211–214. DOI: 10.1109/ICVD.2001.902662Google Scholar
  37. 37.
    Sze V, Chandrakasan A (2007) A 0.4-V UWB baseband processor. In: Proceedings of the ACM/IEEE international symposium on low power electronics and design (ISLPED), pp 262–267. DOI: 10.1145/1283780.1283837Google Scholar
  38. 38.
    Tajalli A, Brauer E, Leblebici Y, Vittoz E (2008) Subthreshold source-coupled logic circuits for ultra-low-power applications. IEEE J Solid State Circuits 43(7):1699–1710. DOI: 10.1109/JSSC.2008.922709CrossRefGoogle Scholar
  39. 39.
    Tajalli A, Leblebici Y (2010) Extreme low-power mixed signal IC design: subthreshold source-coupled circuits. Springer, New YorkCrossRefGoogle Scholar
  40. 40.
    Teichmann P (2012) Adiabatic logic: future trend and system level perspective. Springer, New YorkCrossRefGoogle Scholar
  41. 41.
    Von Arnim K, Borinski E, Seegebrecht P, Fiedler H, Brederlow R, Thewes R, Berthold J, Pacha C (2005) Efficiency of body biasing in 90-nm CMOS for low-power digital circuits. IEEE J Solid State Circuits 40(7):1549–1556. DOI: 10.1109/JSSC.2005.847517CrossRefGoogle Scholar
  42. 42.
    Wang A, Chandrakasan A (2004) A 180 mV FFT processor using subthreshold circuit techniques. In: Proceedings of the IEEE international solid-state circuits conference (ISSCC), pp 292–293. DOI: 10.1109/ISSCC.2004.1332709Google Scholar
  43. 43.
    Wang A, Chandrakasan A (2005) A 180-mV subthreshold FFT processor using a minimum energy design methodology. IEEE J Solid State Circuits 40(1):310–319. DOI: 10.1109/JSSC.2004.837945CrossRefGoogle Scholar
  44. 44.
    Wang JS, Li HY, Yeh C, Chen TF (2005) Design techniques for single-low-Vdd CMOS systems. IEEE J Solid State Circuits 40(5):1157–1165. DOI: 10.1109/JSSC.2005.845979CrossRefGoogle Scholar
  45. 45.
    Wang A, Calhoun B, Chandrakasan A (2006) Sub-threshold design for ultra low-power systems. Springer, New YorkGoogle Scholar
  46. 46.
    Weste N, Harris D (2011) CMOS VLSI design: a circuits and systems perspective, 4th edn. Addison-Wesley, BostonGoogle Scholar
  47. 47.
    Yano K, Yamanaka T, Nishida T, Saito M, Shimohigashi K, Shimizu A (1990) A 3.8-ns CMOS 16x16-b multiplier using complementary pass-transistor logic. IEEE J Solid State Circuits 25(2):388–395. DOI: 10.1109/4.52161CrossRefGoogle Scholar
  48. 48.
    Zhai B, Pant S, Nazhandali L, Hanson S, Olson J, Reeves A, Minuth M, Helfand R, Austin T, Sylvester D, Blaauw D (2009) Energy-efficient subthreshold processor design. IEEE Trans Very Large Scale Integr VLSI Syst 17(8):1127–1137. DOI: 10.1109/TVLSI.2008.2007564CrossRefGoogle Scholar
  49. 49.
    Zhou J, Jayapal S, Busze B, Huang L, Stuyt J (2011) A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library. In: Proceedings of the ACM/EDAC/IEEE design automation conference (DAC), pp 441–446Google Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  • Nele Reynders
    • 1
  • Wim Dehaene
    • 1
  1. 1.ESAT-MICAS, KU LeuvenHeverleeBelgium

Personalised recommendations