Skip to main content
SpringerLink
Log in

Previous Works on Automated Analog IC Sizing

  • Chapter
  • First Online:
AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing

Part of the book series: SpringerBriefs in Applied Sciences and Technology ((BRIEFSINTELL))

Abstract

In the last 25 years, the scientific community proposed many techniques for the automation of analog integrated circuit sizing. In this chapter, those approaches are briefly surveyed, focusing on the optimization techniques that are used. The different approaches are classified in terms of the techniques used and the most significant aspects observed were the setup and the execution time, as well as the accuracy in the evaluation of the solutions. The study is then used to select the optimization methods to be considered in the developed framework.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Barros, M.F.M., Guilherme, J.M.C., Horta, N.C.G.: Analog circuits and systems optimization based on evolutionary computation techniques. Springer, Berlin (2010)

    Book  MATH  Google Scholar 

  2. Makris, C.A., Toumazou, A.C.: Analog IC design automation. II. Automated circuit correction by qualitative reasoning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2), 239–254 (1995)

    Google Scholar 

  3. Toumazou, C., Makris, C.A.: Analog IC design automation. I. Automated circuit generation: new concepts and methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2), 218–238 (1995)

    Article  Google Scholar 

  4. Degrauwe, M.G.R., Nys, O., Dijkstra, E., Rijmenants, J., Bitz, S., Goffart, B.L.A.G., Vittoz, E.A., Cserveny, S., Meixenberger, C., Stappen, G.V.D., Oguey, H.J.: IDAC: an interactive design tool for analog CMOS circuits. IEEE J. Solid-State Circuits 22(6), 1106–1116 (1987)

    Article  Google Scholar 

  5. Horta, N.: Analogue and mixed-signal systems topologies exploration using symbolic methods. Analog Integr. Circ. Sig. Process 31(2), 161–176 (2002)

    Article  Google Scholar 

  6. Koh, H.Y., Sequin, C.H., Gray, P.R.: OPASYN: a compiler for CMOS operational amplifiers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2), 113–125 (1990)

    Article  Google Scholar 

  7. Harvey, J.P., Elmasry, M.I., Leung, B.: STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(11), 1402–1417 (1992)

    Article  Google Scholar 

  8. Maulik, P.C., Carley, L.R., Allstot, D.J.: Sizing of cell-level analog circuits using constrained optimization techniques. IEEE J. Solid-State Circuits 28(3), 223–241 (1993)

    Article  Google Scholar 

  9. Maulik, P.C., Carley, L.R., Rutenbar, R.A.: Integer programming based topology selection of cell-level analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(4), 401–412 (1995)

    Article  Google Scholar 

  10. Matsukawa, K., Morie, T., Tokunaga, Y., Sakiyama, S., Mitani, Y., Takayama, M., Miki, T., Matsumoto, A., Obata, K., Dosho, S.: Design methods for pipeline and delta-sigma A-to-D converters with convex optimization. In: Asia and South Pacific Design Automation Conference, 2009

    Google Scholar 

  11. Hershenson, M.D.M., Boyd, S.P., Lee, T.H.: GPCAD: a tool for CMOS op-amp synthesis. In: IEEE/ACM International Conference on Computer-Aided Design, San Jose, 1998

    Google Scholar 

  12. Kuo-Hsuan, M.: Po-Cheng, P., Hung-Ming, C.: Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping. In: International Symposium on Quality Electronic Design, Santa Clara, 2011

    Google Scholar 

  13. Torralba, A.J., Chavez, J., Franquelo, L.G.: Fuzzy-logic-based analog design tools. Micro, IEEE 16(4), 60–68 (1996)

    Article  Google Scholar 

  14. Torralba, A., Chavez, J., Franquelo, L.G.: FASY: a fuzzy-logic based tool for analog synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7), 705–715 (1996)

    Article  Google Scholar 

  15. Gielen, G.G.E., Walscharts, H.C.C., Sansen, W.M.C.: Analog circuit design optimization based on symbolic simulation and simulated annealing. IEEE J. Solid-State Circuits 25(3), 707–713 (1990)

    Article  Google Scholar 

  16. Ochotta, E.S., Rutenbar, R.A., Carley, L.R.: Synthesis of high-performance analog circuits in ASTRX/OBLX. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(3), 273–294 (1996)

    Article  Google Scholar 

  17. Kruiskamp, W., Leenaerts, D.: DARWIN: CMOS opamp synthesis by means of a genetic algorithm. In: Design Automation Conference, 1995

    Google Scholar 

  18. Doboli, A., Dhanwada, N., Nunez-Aldana, A., Vemuri, R.: A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. ACM Trans. Des. Autom. Electron. Syst. 9(2), 238–271 (2004)

    Article  Google Scholar 

  19. Nagel, L.W.: SPICE2: a computer program to simulate semiconductor circuits. EECS Department, University of California, Berkeley, 1975

    Google Scholar 

  20. Kirkpatrick, S., Gelatt, C.D., Vecchi, M.P.: Optimization by simulated annealing. Science 220(4598), 671–680 (1983)

    Article  MATH  MathSciNet  Google Scholar 

  21. Nye, W., Riley, D., Sangiovanni-Vincentelli, A., Tits, A.: DELIGHT.SPICE: an optimization-based system for the design of integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(4), 501–519 (1988)

    Article  Google Scholar 

  22. Cheng-Wu, L., Pin-Dai, S., Ya-Ting, S., Soon-Jyh, C.: A bias-driven approach for automated design of operational amplifiers. In: International Symposium on VLSI Design, Automation and Test, Hsinchu, 2009

    Google Scholar 

  23. Medeiro, F., Fernandez, F., Dominguez-Castro, R., Rodriguez-Vazquez, A.: A statistical optimization-based approach for automated sizing of analog cells. In: International Conference Computer-Aided Design, 1994

    Google Scholar 

  24. Castro-Lopez, R., Guerra, O., Roca, E., Fernandez, F.: An integrated layout-synthesis approach for analog ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7), 1179–1189 (2008)

    Article  Google Scholar 

  25. Barros, M., Guilherme, J., Horta, N.: Analog circuits optimization based on evolutionary computation techniques. Integr. VLSI J. 43(1), 136–155 (2010)

    Article  Google Scholar 

  26. Barros, M., Guilherme, J., Horta, N.: GA-SVM feasibility model and optimization kernel applied to analog IC design automation. In: ACM Great Lakes symposium on VLSI, Stresa-Lago Maggiore, 2007

    Google Scholar 

  27. Alpaydin, G., Balkir, S., Dundar, G.: An evolutionary approach to automatic synthesis of high-performance analog integrated circuits. IEEE Trans. Evol. Comput. 7(3), 240–252 (2003)

    Article  Google Scholar 

  28. Santos-Tavares, R., Paulino, N., Higino, J., Goes, J., Oliveira, J.P.: Optimization of multi-stage amplifiers in deep-submicron CMOS using a distributed/parallel genetic algorithm. In: International Symposium on Circuits and Systems, Seattle, 2008

    Google Scholar 

  29. Krasnicki, M., Phelps, R., Rutenbar, R., Carley, L.: MAELSTROM: efficient simulation-based synthesis for custom analog cells. In: Design Automation Conference, New Orleans, 1999

    Google Scholar 

  30. Phelps, R., Krasnicki, M., Rutenbar, R., Carley, L., Hellums, J.: Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(6), 703–717 (2000)

    Article  Google Scholar 

  31. Koza, J.R., Bennett, F.I., Andre, D., Keane, M.A., Dunlap, F.: Automated synthesis of analog electrical circuits by means of genetic programming. IEEE Trans. Evol. Comput. 1(2), 109–128 (1997)

    Article  Google Scholar 

  32. Sripramong, T., Toumazou, C.: The invention of CMOS amplifiers using genetic programming and current-flow analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11), 1237–1252 (2002)

    Article  Google Scholar 

  33. Hongying, Y., Jingsong, H.: Evolutionary design of operational amplifier using variable-length differential evolution algorithm. In: International Conference on Computer Application and System Modeling, Taiyuan Shanxi, 2010

    Google Scholar 

  34. Chu, S.-C., Huang, H.-C., Roddick, J.F., Pan, J.-S.: Overview of algorithms for swarm intelligence. In: Computational Collective Intelligence. Technologies and Applications, pp. 28–41. Springer, Berlin Heidelberg (2011)

    Google Scholar 

  35. Gupta, H., Ghosh, B.: Analog Circuits Design Using Ant Colony Optimization. Int. J. Electron. Comput. Commun. Technol. 2(3), 9–21 (2012)

    Google Scholar 

  36. Benhala, B., Ahaitouf, A., Fakhfakh, M., Mechaqrane, A.: New Adaptation of the ACO Algorithm for the Analog Circuits Design Optimization. Int. J. Comput. Sci. Issues 9(3), 360–367 (2012)

    Google Scholar 

  37. Kamisetty, S., Garg, J., Tripathi, J., Mukherjee, J.: Optimization of analog RF circuit parameters using randomness in particle swarm optimization. In: World Congress on Information and Communication Technologies, 2011

    Google Scholar 

  38. Kumar, P.P., Duraiswamy, K.: An optimized device sizing of analog circuits using particle swarm optimization. J. Comput. Sci. 8(6), 930–935 (2012)

    Article  Google Scholar 

  39. Fakhfakh, M., Cooren, Y., Sallem, A., Loulou, M., Siarry, P.: Analog circuit design optimization through the particle swarm optimization technique. Analog Integr. Circ. Sig. Process 63(1), 71–82 (2010)

    Article  Google Scholar 

  40. Lourenço, N., Horta, N.: GENOM-POF: multi-objective evolutionary synthesis of analog ICs with Corners validation. In: Genetic and Evolutionary Computation Conference, Philadelphia, 2012

    Google Scholar 

  41. Lourenço, N., Martins, R., Barros, M., Horta, N.: Analog circuit design based on robust POFs using an enhanced MOEA with SVM models. In: Analog/RF and Mixed-Signal Circuit Systematic Design, pp. 149–167. Springer, Berlin (2013)

    Book  Google Scholar 

  42. McConaghy, T., Palmers, P., Steyaert, M., Gielen, G.: Trustworthy genetic programming-based synthesis of analog circuit topologies using hierarchical domain-specific building blocks. IEEE Trans. Evol. Comput. 15(4), 557–570 (2011)

    Article  Google Scholar 

  43. Pradhan, A., Vemuri, R.: Efficient synthesis of a uniformly spread layout aware pareto surface for analog circuits. In: International Conference on VLSI Design, New Delhi, 2009

    Google Scholar 

  44. Deniz, E., Dundar, G.: Hierarchical performance estimation of analog blocks using Pareto Fronts. In: Ph.D. Research in Microelectronics and Electronics, 2010

    Google Scholar 

  45. Castro-Lopez, R., Roca, E., Fernandez, F.V.: Multimode Pareto fronts for design of reconfigurable analogue circuits. Electron. Lett. 45(2), 95–96 (2009)

    Article  Google Scholar 

  46. Roca, E., Velasco-Jiménez, M., Castro-López, R., Fernández, F.V.: Context-dependent transformation of Pareto-optimal performance fronts of operational amplifiers. Analog Integr. Circ. Sig. Process 73(1), 65–76 (2012)

    Article  Google Scholar 

  47. Gielen, G., McConaghy, T., Eeckelaert, T.: Performance space modeling for hierarchical synthesis of analog integrated circuits. In: Design Automation Conference, 2005

    Google Scholar 

  48. Shoou-Jinn, C., Hao-Sheng, H., Yan-Kuin, S.: Automated passive filter synthesis using a novel tree representation and genetic programming. IEEE Trans. Evol. Comput. 10(1), 93–100 (2006)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Instituto de Telecomunicações, Instituto de Telecomunicações/Instituto, Lisbon, Portugal

    Ricardo Lourenço

  2. Instituto Técnico Superior, Lisbon, Portugal

    Nuno Lourenço

  3. Instituto de Telecomunicacoes ICG-LX, Lisbon, Portugal

    Nuno Horta

Authors
  1. Ricardo Lourenço
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Nuno Lourenço
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Nuno Horta
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Ricardo Lourenço .

Rights and permissions

Reprints and permissions

Copyright information

© 2015 The Author(s)

About this chapter

Cite this chapter

Lourenço, R., Lourenço, N., Horta, N. (2015). Previous Works on Automated Analog IC Sizing. In: AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing. SpringerBriefs in Applied Sciences and Technology(). Springer, Cham. https://doi.org/10.1007/978-3-319-15955-3_2

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-15955-3_2

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-15954-6

  • Online ISBN: 978-3-319-15955-3

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation