Abstract
For the conventional NMOS LC-VCO as shown in Fig. 3.7, a low supply voltage would result in the decrease of the output signal amplitude Vo and thus the degradation of the phase-noise performance since the phase noise is inversely proportional to Vo 2 according to (3.19). For example, if the supply voltage is reduced from 1.2 to 0.3 V, the maximum Vo would roughly decrease from 2.4 to 0.6 V (ignoring the voltage headroom required by the current-biasing transistor). As a result, the minimum achievable phase noise will degrade by 12 dB assuming all other parameters, including the tank capacitance, the tank QT, the oscillation frequency ω 0, and the offset frequency Δω, are kept the same. Such a phase-noise degradation is unacceptable for many cellular standards with stringent phase-noise requirements such as GSM requiring −162 dBc/Hz at 20-MHz frequency offset from a carrier frequency of 900 MHz [1].
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Notes
- 1.
The FoM is still kept the same according to (3.30) since the current to sustain the maximum Vo also reduces by 4 times, and thus the power consumption reduces by 16 times. However, at low supply voltage, even the power budget can be increased, and the phase noise could not be improved anymore since the oscillator would enter the voltage-limited region.
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Luong, H.C., Yin, J. (2016). Ultralow-Voltage VCO and QVCO Using Transformer Technique. In: Transformer-Based Design Techniques for Oscillators and Frequency Dividers. Springer, Cham. https://doi.org/10.1007/978-3-319-15874-7_5
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