Abstract
Arithmetic based on signed-binary number representation is an alternative to carry-save arithmetic. Both offer adders with word-length independent latencies. Comparing both approaches requires optimized adder cells. Small and fast full adder designs have been introduced. A thorough investigation of signed-binary adder cells is still missing. We show that for an example signed-binary encoding scheme the design space consists of 238 different truth tables. Each represents a bit-level signed-binary adder cell. We proposed a new method to enumerate and analyze such a huge design space to gain small area, low power, or low latency signed-binary adder cells and show the limitations of our approach.
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Carter, T.M., Robertson, J.E.: The set theory of arithmetic decomposition. IEEE Trans. Comput. 39, 993–1005 (1990)
Avizienis, A.A. Signed-digit number representations for fast parallel arithmetic. IRE Trans. Electron. Comput. 10(3), 389–400 (1961)
Chow, C.Y., Robertson, J.E.: Logical design of a redundant binary adder. In: Proceedings of the 4th Symposium on Computer Arithmetic, pp. 109–115 (1978)
Zehendner, E.: Reguläre parallele Addierer für redundante binäre Zahlsysteme. Technical Report, Report 255, Institut für Mathematik der University ät Augsburg (1992)
Alioto, M., Palumbo, G.: Analysis and comparison on full adder block in submicron technology. IEEE Trans. Very Large Scale Integr. VLSI Syst. 10(6), 806–823 (2002)
Karnaugh, M.: The map method for synthesis of combinational logic circuits. Trans. AIEE 72(9), 593–599 (1953)
Veitch, E.W.: A chart method for simplifying truth functions. In: Proceedings of the Association for Computing Machinery, Pittsburgh, May 1952, pp. 127–133
Rudell, R.L.: Multiple-Valued Logic Minimization for PLA Syntheis. Technical Report, UCB/ERL M86/65, Electrical Engineering and Computer Science Department, University of California (1986)
Agrawal, P., Agrawal, V.D., Biswas, N.N.: Multiple output minimization. In: Proceedings of the 22nd Design Automation Conference, June 1985, pp. 674–680
Cerny, E., Mange, D., Sanchez, E.: Synthesis of minimal binary decision trees. IEEE Trans. Comput. C-28(7), 472–482 (1979)
Lloris, A., Gomez, J.F., Roman, R.: Using decision trees for the minimization of multiple-valued functions. Int. J. Electron. 75(6), 1035–1041 (1993)
Rushdi, A.M., Ba-Rukab, O.M.: A purely map procedure for two-level multiple-output logic minimization. Int. J. Comput. Math. 84, 1–10 (2007)
Malik, A.A.: Optimization of primitive gate networks using multiple output two-level minimization. In: Proceedings of the 29th ACM/IEEE Design Automation Conference (DAC ’92), pp. 449–453. IEEE Computer Society Press, Los Alamitos (1992)
Kagaris, D., Haniotakis, T.: Transistor-level optimization of supergates. In: Proceedings of 7th International Symposium on Quality Electronic Design (ISQED ’06), March 2006, pp. 685–690
Kagaris, D., Haniotakis, T.: Transistor-level synthesis for low-power applications. In: Proceedings of the 8th International Symposium on Quality Electronic Design (ISQED ’07), March 2007, pp. 607–612
Liu, C.-P.L., Abraham, J.A.: Transistor level synthesis for static cmos combinational circuits. In: Proceedings of the 9th Great Lakes Symposium on VLSI, March 1999, pp. 172–175
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Neuhäuser, D. (2015). Exploring the Design Space of Signed-Binary Adder Cells. In: Mastorakis, N., Bulucea, A., Tsekouras, G. (eds) Computational Problems in Science and Engineering. Lecture Notes in Electrical Engineering, vol 343. Springer, Cham. https://doi.org/10.1007/978-3-319-15765-8_21
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DOI: https://doi.org/10.1007/978-3-319-15765-8_21
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