Abstract
This paper presents a flexible architecture for a GPS receiver using Partial Reconfiguration (PR) on a System on Chip (SoC) device consisting on an FPGA and two ARM cores. With built-in error-correction techniques offered by modern SOCs, this device meets the requirements of a Brazilian nanosatellite for CONASAT constellation. This receiver benefits from PR, thereby increasing system performance, hardware sharing, and power consumption optimization, among others. Additionally, all the advantages favor in-orbit reconfiguration. The proposed architecture, as requested, uses COTS components.
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Albuquerque, G.L.A., Carvalho, M.J.M., Valderrama, C. (2016). Brazilian Nano-satellite with Reconfigurable SOC GNSS Receiver Tracking Capability. In: Kastensmidt, F., Rech, P. (eds) FPGAs and Parallel Architectures for Aerospace Applications. Springer, Cham. https://doi.org/10.1007/978-3-319-14352-1_2
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DOI: https://doi.org/10.1007/978-3-319-14352-1_2
Publisher Name: Springer, Cham
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Online ISBN: 978-3-319-14352-1
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