Abstract
With the development of new technologies, the operating frequencies on chip are increasing at a faster rate, such as computational methods, utilization of high-frequency clocks, digital circuits, etc. The process-technology-independent I/O standard, low-voltage differential signaling (LVDS), is basically developed for low-voltage, low-power, low-noise, and high-speed I/O interfaces. Low power is owing to the use of very small differential swing, while low noise is owing to essential nature of the differential circuits. Based upon ANSI TIA/EIA-644 LVDS standard, this paper presents a low-voltage and high-speed LVDS driver. A Common-mode feedback (CMFB) and a pull-up/down circuits were suggested as carried out by a standard 0.35-μm complementary metal oxide semiconductor (CMOS) process with a die area of 0.115 mm2. The measured results present that the driver works well at 1.5 Gbps, and the static current is less than 11.5 mA under 3.3 V.
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© 2015 Springer International Publishing Switzerland
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Wang, Z., Guo, A., Pu, Y. (2015). A High-Speed LVDS Driver Design in 0.35-μm CMOS Technology. In: Wang, W. (eds) Proceedings of the Second International Conference on Mechatronics and Automatic Control. Lecture Notes in Electrical Engineering, vol 334. Springer, Cham. https://doi.org/10.1007/978-3-319-13707-0_110
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DOI: https://doi.org/10.1007/978-3-319-13707-0_110
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