Abstract
As today’s high performance embedded systems are heterogeneous platforms, a crisp boundary between the software and the hardware ciphers is fast getting murky. This work takes up the design of a dedicated hardware accelerator for HC-128, one of the stream ciphers in the software portfolio of eSTREAM finalists. We discuss a novel idea of splitting states kept in SRAMs into multiple smaller SRAMs and exploit the increased parallel accesses to achieve higher throughput. We optimize the accelerator design with state splitting by different factors. A detailed throughput-area-power analysis of these design points follow along with a benchmarking with the state-of-the-art for HC-128. Our implementation marks an HC-128 ASIC with the highest throughput per area performance reported in the literature till date.
Prasanna Ravi: This work was done in part while the second author was visiting RWTH Aachen as a DAAD summer intern.
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Khalid, A., Ravi, P., Chattopadhyay, A., Paul, G. (2014). One Word/Cycle HC-128 Accelerator via State-Splitting Optimization. In: Meier, W., Mukhopadhyay, D. (eds) Progress in Cryptology -- INDOCRYPT 2014. INDOCRYPT 2014. Lecture Notes in Computer Science(), vol 8885. Springer, Cham. https://doi.org/10.1007/978-3-319-13039-2_17
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DOI: https://doi.org/10.1007/978-3-319-13039-2_17
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