Building Dependable Electronic Systems for Autonomous Maintenance

Part of the Decision Engineering book series (DECENGIN)


Maintenance repair and overhaul (MRO) of high value systems is expensive, time consuming and relies heavily upon back-to-base repair and overhaul activity. Autonomous maintenance of repairable systems is a rapidly developing area in through-life engineering services that specifically aims to reduce both mean time to repair and frequency of preventative maintenance. Modern engineering systems must perform reliably in the event of random upset events that threaten to induce malfunction or unpredictable behavior. These requirements are fuelling the integration of fault-tolerant and self-repairing techniques into electronic systems at design time. This chapter investigates emerging techniques being utilised in electronics that bring new self-repair capability to high-value applications such as aviation, land vehicles, renewable energy and space exploration. The cost/benefit trade-off of self-repair strategies is analysed in terms of redundant resource allocation and key performance metrics. The potential for future uptake is discussed in the context of current and next-generation platforms.


  1. 1.
    Cheatham JA, Emmert JM, Baumgart S (2006) A survey of fault tolerant methodologies for FPGAs. ACM Trans Des Autom Electron Syst. 11(2):501–533. doi:10.1145/1142155.1142167 CrossRefGoogle Scholar
  2. 2.
    Morgan KS, McMurtrey DL, Pratt BH, Wirthlin MJ (2007) A Comparison of TMR With Alternative Fault-Tolerant Design Techniques for FPGAs. IEEE Trans Nucl Sci 54(6):2065–2072. doi:10.1109/TNS.2007.910871 CrossRefGoogle Scholar
  3. 3.
    Evans AC (1999) Applications of semiconductor test economics, and multisite testing to lower cost of test. In: IEEE proceedings of international test conference. doi:10.1109/TEST.1999.805620
  4. 4.
    Walter JD (2003) Methods to account for accelerated semi-conductor device wear out in longlife aerospace applications. DTIC document, VirginiaGoogle Scholar
  5. 5.
    White M (2010) Scaled cmos technology reliability users guide.
  6. 6.
    Sexton FW (2003) Destructive single-event effects in semiconductor devices and ICs. IEEE Trans Nucl Sci 50(3):603–621. doi:10.1109/TNS.2003.813137 CrossRefGoogle Scholar
  7. 7.
    (2007) Radiation Effects on Embedded Systems, 1 edn. Springer, BerlinGoogle Scholar
  8. 8.
    Nicolaidis M (2010) Soft errors in modern electronic systems. Springer, BerlinGoogle Scholar
  9. 9.
    Von Neumann J (1956) Probabilistic logics and the synthesis of reliable organisms from unreliable components. Automata studies 34:43–98Google Scholar
  10. 10.
    El-Maleh AH, Al-Hashimi BM, Melouki A, Khan F (2009) Defect-tolerant n2-transistor structure for reliable nanoelectronic designs. IET Comput Digital Tech 3(6):570–580. doi:10.1049/iet-cdt.2008.0133 CrossRefGoogle Scholar
  11. 11.
    Lyons RE, Vanderkulk W (1962) The use of triple-modular redundancy to improve computer reliability. IBM J Res Dev 6(2):200–209. doi:10.1147/rd.62.0200 CrossRefMATHGoogle Scholar
  12. 12.
    Parris MG, Sharma CA, Demara RF (2011) Progress in autonomous fault recovery of field programmable gate arrays. ACM Comput Surv 43(4):31. doi:10.1145/1978802.1978810 CrossRefGoogle Scholar
  13. 13.
    Emmert JM, Stroud CE, Abramovici M (2007) Online fault tolerance for FPGA logic blocks. IEEE Trans Very Large Scale Integr (VLSI) Syst 15(2):216–226. doi:10.1109/TVLSI.2007.891102 CrossRefGoogle Scholar
  14. 14.
    Breuer MA, Gupta SK, Mak TM (2004) Defect and error tolerance in the presence of massive numbers of defects. IEEE Des Test Comput 21(3):216–227. doi:10.1109/MDT.2004.8 CrossRefGoogle Scholar
  15. 15.
    Han J, Gao J, Jonker P, Qi Y, Fortes JAB (2005) Toward hardware-redundant, fault-tolerant logic for nanoelectronics. IEEE Des Test Comput 22(4):328–339. doi:10.1109/MDT.2005.97 CrossRefGoogle Scholar
  16. 16.
    Wadsack RL (1978) Fault modeling and logic simulation of CMOS and M08 integrated circuits. Bell Syst Tech J 57(5):1449–1474CrossRefMATHGoogle Scholar
  17. 17.
    Kothe R, Vierhaus HT, Coym T, Vermeiren W, Straube B (2006) Embedded self repair by transistor and gate level reconfiguration. In: Design and diagnostics of electronic circuits and systems, IEEE. doi:10.1109/DDECS.2006.1649613
  18. 18.
    Jones D, McWilliam R, Purvis A (2008) Designing convergent cellular automata. Biosystems 96:80–85CrossRefGoogle Scholar
  19. 19.
    Wendling X, Rochet R, Leveugle R (1996) ROM-based synthesis of fault-tolerant controllers. In: IEEE international symposium on defect and fault tolerance in VLSI systemsGoogle Scholar
  20. 20.
    Gerbaux L, Saucier G (1992) Automatic synthesis of large Moore sequencers. Integr VLSI J 13(3):259–281. doi:10.1016/0167-9260(92)90031-S CrossRefGoogle Scholar
  21. 21.
    Moreno G, Civit-Balcells A, Guerra-Gutierrez P (2007) ROM-based finite state machine implementation in low cost FPGAs. In: IEEE international symposium on industrial electronicsGoogle Scholar
  22. 22.
    Rochet R, Leveugle R, Saucier G (1993) Analysis and comparison of fault tolerant FSM architecture based on SEC codes. In: IEEE international workshop on defect and fault tolerance in VLSI systemsGoogle Scholar
  23. 23.
    Walker JA, Trefzer MA, Bale SJ, Tyrrell AM (2013) PAnDA: a reconfigurable architecture that adapts to physical substrate variations. IEEE Trans Comput 62(8):1584–1596. doi:10.1109/TC.2013.59 CrossRefMathSciNetGoogle Scholar
  24. 24.
    Basha C, Pillement S, Lagadec L New reconfigurable fault tolerant FPGA architecture: a design for mission critical applications. 8th HiPEAC workshop on reconfigurable computing, Vienna, Austria, Jan 20–22Google Scholar
  25. 25.
    Frei R, McWilliam R, Derrick B, Purvis A, Tiwari A, Serugendo GDM (2013) Self-healing and self-repairing technologies. Int J Adv Manufact Technol 69:1033–1061. doi:10.1007/s00170-013-5070-2 CrossRefGoogle Scholar
  26. 26.
    Campregher N, Cheung PYK, Constantinides GA, Vasilko M (2006) Reconfiguration and fine-grained redundancy for fault tolerance in FPGAs. In: International conference on field programmable logic and applications (FPL ‘06)Google Scholar
  27. 27.
    Stott E, Sedcole P, Cheung P (2008) Fault tolerant methods for reliability in FPGAs. In: International conference on field programmable logic and applications (FPL ‘08)Google Scholar
  28. 28.
    Zhang K, Bedette G, DeMara RF (2006) Triple modular redundancy with standby (TMRSB) supporting dynamic resource reconfiguration. In: IEEE autotestconGoogle Scholar
  29. 29.
    McCluskey EJ, Bozorgui-Nesbat S (1981) Design for autonomous test. IEEE Trans Circuits Syst 28(11):1070–1079. doi:10.1109/TCS.1981.1084930 CrossRefGoogle Scholar
  30. 30.
    Quinn HM, Black DA, Robinson WH, Buchner SP (2013) Fault simulation and emulation tools to augment radiation-hardness assurance testing. IEEE Trans Nucl Sci 60(3):2119–2142. doi:10.1109/TNS.2013.2259503 CrossRefGoogle Scholar
  31. 31.
    Sedmark RM (1994) Boundary-scan: beyond production test. In: 12th IEEE VLSI test symposiumGoogle Scholar
  32. 32.
    Arlat J, Aguera M, Amat L, Crouzet Y, Fabre JC, Laprie JC et al (1990) Fault injection for dependability validation: a methodology and some applications. IEEE Trans Software Eng 16(2):166–182. doi:10.1109/32.44380 CrossRefGoogle Scholar
  33. 33.
    Goyal A, Swaminathan M, Chatterjee A, Howard DC, Cressler JD (2012) A new self-healing methodology for rf amplifier circuits based on oscillation principles. IEEE Trans VLSI Syst 20(10):1835–1848. doi:10.1109/Tvlsi.2011.2163953 CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  • Richard McWilliam
    • 1
  • Philipp Schiefer
    • 1
  • Alan Purvis
    • 1
  1. 1.Centre for Electronic Systems, School of Engineering and Computing Sciences, Science LaboratoriesDurham UniversityDurhamUK

Personalised recommendations