Timed Automata Verification via IC3 with Zones

  • Tobias Isenberg
  • Heike Wehrheim
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8829)


Timed automata are a formal method for the modelling of real-time systems. With a large number of sophisticated tools, ample support for not only specification but also verification is available today. However, although all these tools are highly optimized, verification of timed automata, in particular networks of timed automata, remains challenging. This is due to the large amount of memory needed for storing automata states.

In this paper, we present a new approach to timed automata verification based on the SAT-based induction method IC3. Unlike previous work on extending IC3 to timed systems, we employ zones, not regions, for the symbolic representation of timed automata states. While this complicates a timed IC3 procedure, specifically, necessitates the computation of a zone from possibly infinitely many counterexamples to induction, it pays off with respect to memory consumption. Experimental results show that our approach can outperform Uppaal for networks with large numbers of timed automata.


Verification timed automata zone abstraction IC3 SMT 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Alur, R., Dill, D.: Automata for modeling real-time systems. In: Paterson, M. (ed.) ICALP 1990. LNCS, vol. 443, pp. 322–335. Springer, Heidelberg (1990)CrossRefGoogle Scholar
  2. 2.
    Alur, R., Dill, D.L.: A theory of timed automata. Theoretical Computer Science 126(2), 183–235 (1994)MathSciNetCrossRefMATHGoogle Scholar
  3. 3.
    Baumgartner, J., Ivrii, A., Matsliah, A., Mony, H.: IC3-guided abstraction. In: Cabodi, G., Singh, S. (eds.) FMCAD, pp. 182–185. IEEE (2012)Google Scholar
  4. 4.
    Behrmann, G., Bouyer, P., Larsen, K.G., Pelánek, R.: Lower and upper bounds in zone-based abstractions of timed automata. Int. J. Softw. Tools Technol. Transf. 8(3), 204–215 (2006)CrossRefGoogle Scholar
  5. 5.
    Behrmann, G., Larsen, K.G., Pearson, J., Weise, C., Yi, W.: Efficient timed reachability analysis using clock difference diagrams. In: Halbwachs, N., Peled, D.A. (eds.) CAV 1999. LNCS, vol. 1633, pp. 341–353. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  6. 6.
    Bengtsson, J., Larsen, K.G., Larsson, F., Pettersson, P., Yi, W.: Uppaal — a Tool Suite for Automatic Verification of Real–Time Systems. In: Alur, R., Sontag, E.D., Henzinger, T.A. (eds.) HS 1995. LNCS, vol. 1066, pp. 232–243. Springer, Heidelberg (1996)CrossRefGoogle Scholar
  7. 7.
    Bengtsson, J., Yi, W.: Timed automata: Semantics, algorithms and tools. In: Desel, J., Reisig, W., Rozenberg, G. (eds.) Lectures on Concurrency and Petri Nets. LNCS, vol. 3098, pp. 87–124. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  8. 8.
    Beyer, D., Lewerentz, C., Noack, A.: Rabbit: A tool for BDD-based verification of real-time systems. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 122–125. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  9. 9.
    Bouyer, P.: From Qualitative to Quantitative Analysis of Timed Systems. Mémoire d’habilitation, Université Paris 7, Paris, France (January 2009)Google Scholar
  10. 10.
    Bozga, M., Daws, C., Maler, O., Olivero, A., Tripakis, S., Yovine, S.: Kronos: A model-checking tool for real-time systems. In: Vardi, M.Y. (ed.) CAV 1998. LNCS, vol. 1427, pp. 546–550. Springer, Heidelberg (1998)CrossRefGoogle Scholar
  11. 11.
    Bradley, A.R.: SAT-based model checking without unrolling. In: Jhala, R., Schmidt, D. (eds.) VMCAI 2011. LNCS, vol. 6538, pp. 70–87. Springer, Heidelberg (2011)CrossRefGoogle Scholar
  12. 12.
    Cimatti, A., Griggio, A.: Software model checking via IC3. In: Madhusudan, P., Seshia, S.A. (eds.) CAV 2012. LNCS, vol. 7358, pp. 277–293. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  13. 13.
    Dijkstra, E.: Guarded commands, nondeterminacy, and formal derivation of programs. In: Gries, D. (ed.) Programming Methodology, pp. 166–175. Springer, New York (1978)CrossRefGoogle Scholar
  14. 14.
    Dill, D.L.: Timing assumptions and verification of finite-state concurrent systems. In: Sifakis, J. (ed.) CAV 1989. LNCS, vol. 407, pp. 197–212. Springer, Heidelberg (1990)CrossRefGoogle Scholar
  15. 15.
    Een, N., Mishchenko, A., Brayton, R.: Efficient implementation of property directed reachability. In: Proceedings of the International Conference on Formal Methods in Computer-Aided Design, FMCAD 2011, pp. 125–134. FMCAD Inc., Austin (2011)Google Scholar
  16. 16.
    Hassan, Z., Bradley, A., Somenzi, F.: Better generalization in IC3. In: Formal Methods in Computer-Aided Design (FMCAD), pp. 157–164 (October 2013)Google Scholar
  17. 17.
    Kindermann, R., Junttila, T., Niemelä, I.: Beyond Lassos: Complete SMT-Based Bounded Model Checking for Timed Automata. In: Giese, H., Rosu, G. (eds.) FORTE 2012 and FMOODS 2012. LNCS, vol. 7273, pp. 84–100. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  18. 18.
    Kindermann, R., Junttila, T., Niemelä, I.: SMT-Based Induction Methods for Timed Systems. In: Jurdziński, M., Ničković, D. (eds.) FORMATS 2012. LNCS, vol. 7595, pp. 171–187. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  19. 19.
    de Moura, L., Bjørner, N.S.: Z3: An efficient SMT solver. In: Ramakrishnan, C.R., Rehof, J. (eds.) TACAS 2008. LNCS, vol. 4963, pp. 337–340. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  20. 20.
    Nguyen, T.K., Sun, J., Liu, Y., Dong, J.S., Liu, Y.: Improved BDD-based discrete analysis of timed systems. In: Giannakopoulou, D., Méry, D. (eds.) FM 2012. LNCS, vol. 7436, pp. 326–340. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  21. 21.
    Suda, M.: Triggered Clause Pushing for IC3. ArXiv e-prints (July 2013)Google Scholar
  22. 22.
    Sun, J., Liu, Y., Dong, J.S., Pang, J.: Pat: Towards flexible verification under fairness. In: Bouajjani, A., Maler, O. (eds.) CAV 2009. LNCS, vol. 5643, pp. 709–714. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  23. 23.
    Wang, F.: Symbolic verification of complex real-time systems with clock-restriction diagram. In: Kim, M., Chin, B., Kang, S., Lee, D. (eds.) FORTE. IFIP Conference Proceedings, vol. 197, pp. 235–250. Kluwer (2001)Google Scholar
  24. 24.
    Wang, F., Wu, R.S., Huang, G.D.: Verifying timed and linear hybrid rule-systems with RED. In: Chu, W.C., Juzgado, N.J., Wong, W.E. (eds.) SEKE, pp. 448–454 (2005)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Tobias Isenberg
    • 1
  • Heike Wehrheim
    • 1
  1. 1.Institut für InformatikUniversität PaderbornPaderbornGermany

Personalised recommendations