Abstract
Effective fault-tolerant techniques are essential for improving the reliability of multiprocessor systems. This paper investigates the fault-tolerance of torus-connected VLSI array using pre-integrated spare processing elements (PEs), by reconfiguring the interconnection network among all PEs. We model the problem of whether all faulty PEs can be replaced by spare ones as the problem of finding maximum independent set for a contradiction graph, which is constructed from the original physical arrays with faulty PEs. Each node of the graph represents an alternative of a faulty PE, while an edge denotes that different alternatives cannot coexist. We propose efficient algorithms to construct contradiction graphs from physical arrays with faulty PEs and redundant PEs. We then customize an ant-colony algorithm to find independent set as large as possible. We develop an efficient algorithm to generate logic arrays based on the produced independent set. Three different distributions of redundant PEs are discussed in this paper, and satisfactory results have been achieved in simulation.
This work was supported by the National Natural Science Foundation of China under Grant No. 61173032, and the Doctoral Fund of Ministry of Education of China under Grant No. 20100032110041 and No. 20131201110002.
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Zhu, L., Wu, J., Jiang, G., Sun, J. (2014). Interconnection Network Reconstruction for Fault-Tolerance of Torus-Connected VLSI Array. In: Sun, Xh., et al. Algorithms and Architectures for Parallel Processing. ICA3PP 2014. Lecture Notes in Computer Science, vol 8630. Springer, Cham. https://doi.org/10.1007/978-3-319-11197-1_22
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DOI: https://doi.org/10.1007/978-3-319-11197-1_22
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-11196-4
Online ISBN: 978-3-319-11197-1
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