Speculative Program Parallelization with Scalable and Decentralized Runtime Verification

  • Aravind Sukumaran-Rajam
  • Juan Manuel Martinez Caamaño
  • Willy Wolff
  • Alexandra Jimborean
  • Philippe Clauss
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8734)


Thread Level Speculation (TLS) is a dynamic code parallelization technique proposed to keep the software in pace with the advances in hardware, in particular, to automatically parallelize programs to take advantage of the multi-core processors. Being speculative, frameworks of this type unavoidably rely on verification systems that are similar to software transactional memory, and that require voluminous inter-thread communications or centralized registering of the performed memory accesses. The high degree of communication is against the basic principles of high performance parallel computing, does not scale with an increasing number of processor cores, and yields weak performance. Moreover, TLS systems often apply one unique parallelization strategy consisting in slicing a loop into several parallel speculative threads. Such a strategy is also against the basic principles since loops in the original serial code are not necessarily parallel and also, it is well-known that the parallel schedule must promote data locality which is crucial in obtaining good performance. This situation appeals to scalable and decentralized verification systems and new strategies to dynamically generate efficient parallel code resulting from advanced optimizing parallelizing transformations. Such transformations require a more complex verification system that allows intra-thread iterations to be reordered. In this paper, we propose a verification system of this kind, based on a model built at runtime and predicting a linear memory behavior. This strategy is part of the Apollo speculative code parallelizer which is based on an adaptation for dynamic usage of the polyhedral model.


Loop Nest Benchmark Suite Parallel Code Memory Instruction Loop Bound 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Rauchwerger, L., Padua, D.: The LRPD test: speculative run-time parallelization of loops with privatization and reduction parallelization. In: PLDI 1995. ACM (1995)Google Scholar
  2. 2.
    Liu, W., Tuck, J., Ceze, L., Ahn, W., Strauss, K., Renau, J., Torrellas, J.: POSH: a TLS compiler that exploits program structure. In: PPoPP 2006. ACM (2006)Google Scholar
  3. 3.
    Raman, E., Vachharajani, N., Rangan, R., August, D.I.: Spice: speculative parallel iteration chunk execution. In: CGO 2008. ACM (2008)Google Scholar
  4. 4.
    Johnson, T.A., Eigenmann, R., Vijaykumar, T.N.: Speculative thread decomposition through empirical optimization. In: PPoPP 2007. ACM (2007)Google Scholar
  5. 5.
    Feautrier, P., Lengauer, C.: Polyhedron model. In: Padua, D. (ed.) Encyclopedia of Parallel Computing, pp. 1581–1592. Springer, US (2011)Google Scholar
  6. 6.
    Shun, J., Blelloch, G.E., Fineman, J.T., Gibbons, P.B., Kyrola, A., Simhadri, H.V., Tangwongsan, K.: Brief announcement: the problem based benchmark suite. In: SPAA 2012. ACM (2012)Google Scholar
  7. 7.
    Bondhugula, U., Hartono, A., Ramanujam, J., Sadayappan, P.: A practical automatic polyhedral parallelizer and locality optimizer. In: PLDI 2008. ACM (2008)Google Scholar
  8. 8.
    Jimborean, A., Clauss, P., Dollinger, J.F., Loechner, V., Juan Manuel, M.: Dynamic and Speculative Polyhedral Parallelization Using Compiler-Generated Skeletons. International Journal of Parallel Programming 42(4), 529–545 (2014)CrossRefGoogle Scholar
  9. 9.
    LLVM: LLVM compiler infrastructure,
  10. 10.
    Banerjee, U.: Loop Transformations for Restructuring Compilers - The Foundations. Kluwer Academic Publishers (1993)Google Scholar
  11. 11.
    Oancea, C.E., Mycroft, A., Harris, T.: A lightweight in-place implementation for software thread-level speculation. In: SPAA 2009. ACM (2009)Google Scholar
  12. 12.
    Yiapanis, P., Rosas-Ham, D., Brown, G., Luján, M.: Optimizing software runtime systems for speculative parallelization. ACM TACO 9(4), 39:1–39:27 (2013)Google Scholar
  13. 13.
    Bruening, D., Devabhaktuni, S., Amarasinghe, S.: Softspec: Software-based speculative parallelism. In: Workshop on Feedback-Directed and Dynamic Optimization 2000. ACM (2000)Google Scholar
  14. 14.
    Süßkraut, M., Weigert, S., Schiffel, U., Knauth, T., Nowack, M., de Brum, D.B., Fetzer, C.: Speculation for parallelizing runtime checks. In: Guerraoui, R., Petit, F. (eds.) SSS 2009. LNCS, vol. 5873, pp. 698–710. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  15. 15.
    Steffan, J.G., Colohan, C.B., Zhai, A., Mowry, T.C.: A scalable approach to thread-level speculation. In: ISCA 2000. ACM (2000)Google Scholar
  16. 16.
    Kim, H., Johnson, N.P., Lee, J.W., Mahlke, S.A., August, D.I.: Automatic speculative doall for clusters. In: CGO 2012. ACM (2012)Google Scholar
  17. 17.
    Adl-Tabatabai, A.R., Lewis, B.T., Menon, V., Murphy, B.R., Saha, B., Shpeisman, T.: Compiler and runtime support for efficient software transactional memory. In: PLDI 2006 (2006)Google Scholar
  18. 18.
    Mehrara, M., Hao, J., Hsu, P.C., Mahlke, S.: Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory. SIGPLAN Not. 44(6), 166–176 (2009)CrossRefGoogle Scholar
  19. 19.
    Raman, A., Kim, H., Mason, T.R., Jablin, T.B., August, D.I.: Speculative parallelization using software multi-threaded transactions. In: ASPLOS 2010. ACM (2010)Google Scholar
  20. 20.
    Che, S., Boyer, M., Meng, J., Tarjan, D., Sheaffer, J.W., Lee, S.H., Skadron, K.: Rodinia: A benchmark suite for heterogeneous computing. In: IISWC 2009. IEEE (2009)Google Scholar
  21. 21.
    Stratton, J.A., Rodrigues, C., Sung, I.J., Obeid, N., Chang, L.W., Anssari, N., Liu, G.D.: mei W. Hwu, W.: The Parboil technical report. Technical report, IMPACT Technical Report, IMPACT-12-01, University of Illinois, at Urbana-Champaign (2012)Google Scholar
  22. 22.

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Aravind Sukumaran-Rajam
    • 1
  • Juan Manuel Martinez Caamaño
    • 1
  • Willy Wolff
    • 1
  • Alexandra Jimborean
    • 2
  • Philippe Clauss
    • 1
  1. 1.INRIA, Team CAMUS, ICube Lab, CNRSUniversity of StrasbourgFrance
  2. 2.Department of Information TechnologyUppsala UniversitySweden

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