Abstract
This work proposes a logically optimized smallest arithmetic architecture for the new Secure Hash Algorithm-3 (SHA-3) core using the Look-Up-Table (LUT) resources of FPGA. In this work a novel technique for compact implementation of SHA-3 core is discussed. The Logical operations of the SHA-3 core are optimized using Boolean equations and the result is saved in LUT_6 primitives available in modern Xilinx FPGAs. The proposed architecture consists of 64 LUT_6 primitives and these LUTs are used throughout the compression function operation. Work is still in progress on control circuitry in which we are trying to access internal resources of FPGA. So results of only Core implantation are discussed now and will be updated after designing of control circuitry.
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References
Wang, X., Feng, D., Lai, X., Yu, H.: Collisions for hash functions MD4, MD5, HAVAL-128 and RIPEMD. Cryptology ePrint Archive, Report 2004/199, pp. 1–4 (2004). http://eprint.iacr.org/2004/199
Szydlo, M.: SHA-1 collisions can be found in 263 operations. CryptoBytes, Technical Newsletter (2005). http://www.rsa.com/rsalabs/node.asp?id=2927
Stevens, M.: Fast collision attack on MD5. ePrint-2006-104, pp. 1–13 (2006). http://eprint.iacr.org/2006/104.pdf
Federal Register, Vol. 72, No. 212, Friday, November 2 (2007), Notices. http://csrc.nist.gov/groups/ST/hash/documents/FR_Notice_Nov07.pdf
National Institute of Standards and Technology (NIST): SHA-3 Winner announcement. http://www.nist.gov/itl/csd/sha-100212.cfm
Latif, K., Rao, M., Aziz, A., Mahboob, A.: Efficient hardware implementations and hardware performance evaluation of SHA-3 finalists. In: NIST third SHA-3 Candidate Conference, Washington D.C., 22–23 March 2012
Provelengios, G., Kitsos, P., Sklavos, N., Koulamas, C.: FPGA-based design approaches of Keccak hash function. In: 2012 15th Euromicro Conference on Digital System Design (DSD), pp. 648, 653, 5–8 Sept 2012. doi:10.1109/DSD.2012.63
Homsirikamol, E., Rogawsk, M., Gaj, K.: Comparing hardware performance of round 3 SHA-3 candidates using multiple hardware architectures in Xilinx and Altera FPGAs. In: ECRYPT II Hash Workshop 2011, Tallinn, Estonia, 19–20 May, pp. 1–15 (2011)
Latif, K., Aziz, A., Mahboob, A.: Optimal utilization of available reconfigurable hardware resources. Elsevier’s Comput. Electr. Eng. 37(6), 1043–1057 (2011)
Bertoni, G., Daemen, J., Peeters, M., Assche, G.: The Keccak SHA-3 submission version 3, pp. 1–14, (2011). http://keccak.noekeon.org/Keccak-reference-3.0.pdf
Gaj, K., Homsirikamol, E., Rogawsk, M., Shahid, R., Sharif, M.: Comprehensive evaluation of high speed and medium speed implementations of five SHA-3 finalist using Xilinx and Altera FPGAs. In: SHA-3 Conference (2012)
Kaps, J., Yalla, P., Surapathi, K., Habib, B., Vadlamudi, S., Gurung, S.: Lightweight implementations of SHA-3 finalists on FPGAs. In: SHA-3 Conference (2012)
Jungk, B.: Evaluation of compact FPGA implementations for all SHA-3 finalists. In: SHA-3 Conference 2012
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Rao, M., Newe, T., Aziz, A. (2014). Logically Optimized Smallest FPGA Architecture for SHA- 3 Core. In: Shaikh, F., Chowdhry, B., Zeadally, S., Hussain, D., Memon, A., Uqaili, M. (eds) Communication Technologies, Information Security and Sustainable Development. IMTIC 2013. Communications in Computer and Information Science, vol 414. Springer, Cham. https://doi.org/10.1007/978-3-319-10987-9_18
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DOI: https://doi.org/10.1007/978-3-319-10987-9_18
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