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Memory-Based Logic Control for Embedded Systems

  • Václav DvořákEmail author
  • Petr Mikušek
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 325)

Abstract

Implementation of logic control algorithms in embedded systems is limited by space and response time. Use of a single look-up table (LUT) for multiple-output Boolean function is almost always excluded due to the LUT size. The paper deals with implementation in a form of cascade of smaller LUTs with response time given by a series of few look-ups. Cascade length and memory required to store LUTs can be varied and it is shown that an optimal trade-offs can be reached. Changes in logic control can be implemented easily by re-loading data into LUTs. The presented method is thus useful for logic control in embedded systems or in microcontroller software.

Keywords

Logic control Multiple-output logic functions Look-up table (LUT) cascades Embedded systems 

Notes

Acknowledgments

This research has been carried out under the financial support of the research grants “Natural Computing on Unconventional Platforms”, GAČR GP103/10/1517, and “Security-Oriented Research in Information Technology”, the research plan MSM0021630528.

References

  1. 1.
    Sasao, T., Matsuura, M., and Iguchi, Y.: A cascade realization of multiple-output function for reconfigurable hardware. In: International Workshop on Logic and Synthesis IWLS01, pp. 225–230. Lake Tahoe, CA (2001)Google Scholar
  2. 2.
    Nakahara, H., Sasao, T., and Matsuura, M.: A comparison of architectures for various decision diagram machines. In: International Symposium on Multiple-Valued Logic, pp. 229–234. IEEE CS Press, Barcelona (2001)Google Scholar
  3. 3.
    Nakahara, H., Sasao, T., Matsuura, M., Kawamura: A parallel branching program machine for sequential circuits: Implementation and evaluation. IEICE Transactions on Information and Systems, E93-D, pp. 2048–2058 (2010)Google Scholar
  4. 4.
    Mikušek, P., Dvořák, V.: On lookup table Cascade-based realizations of arbiters. In: Proceedings of the 11th EUROMICRO Conference on Digital System Design DSD, pp. 795–802. IEEE CS Press, Parma (2008)Google Scholar
  5. 5.
    Brzozowski, J. A., Luba, T.: Decomposition of boolean functions specified by cubes. Research report CS-97-01, University of Waterloo, Canada (1997)Google Scholar
  6. 6.
    Nakahara, H., Sasao.: A method to decompose multiple-output logic functions. In: 41st Design Automation Conference DAC, pp. 428–433. IEEE Press, San Diego (2004)Google Scholar
  7. 7.
    Dvořák, V., Mikušek, P.: On the cascade realization of sparse logic functions, In: Proceedings of the 14th EUROMICRO Conference on Digital System Design DSD, pp. 21–28. IEEE CS Press, Oulu (2011)Google Scholar
  8. 8.
    Drechsler, R., Becker, B.: Binary Decision Diagrams-Theory and Implementation. Kluwer Academic Publishers, Boston (1998)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.Faculty of Information TechnologyBrno University of TechnologyBrnoCzech Republic

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