On-Chip Protection Solution for Radio Frequency Integrated Circuits in Standard CMOS Process

Abstract

Standard CMOS technologies have been increasingly used in RF IC applications mainly due to low manufacture cost and improvement in performance. Achieving sufficient ESD protection for RF and high-speed mixed signal ICs using mainstream CMOS processes imposes a major design and reliability challenge. Ideally ESD protection must be transparent to the protected core circuitry under normal operation conditions. In reality, interaction always exists between the ESD protection structures and the core circuits under protection due to parasitic resistance and capacitance associated with the ESD protection. Such parasitic may be tolerable in IC chips that operate in lower frequency. ESD protection devices for RF applications must hold very low parasitic capacitance to minimize degradation to RF functionality from poor input/output impedance matching. This requirement poses one of greatest challenges in RF ESD design, as a low capacitance typically means a small device area and consequently a poor robustness of the ESD protection device. Other concerns in ESD design for RF ICs include the signal distortion due to the nonlinearity of the parasitic capacitance, the noise coupling as well as noise generation through the ESD protection structures.