Advertisement

Binary Decision Diagrams

  • Randal E. Bryant
Chapter

Abstract

Binary decision diagrams provide a data structure for representing and manipulating Boolean functions in symbolic form. They have been especially effective as the algorithmic basis for symbolic model checkers. A binary decision diagram represents a Boolean function as a directed acyclic graph, corresponding to a compressed form of decision tree. Most commonly, an ordering constraint is imposed among the occurrences of decision variables in the graph, yielding ordered binary decision diagrams (OBDD). Representing all functions as OBDDs with a common variable ordering has the advantages that (1) there is a unique, reduced representation of any function, (2) there is a simple algorithm to reduce any OBDD to the unique form for that function, and (3) there is an associated set of algorithms to implement a wide variety of operations on Boolean functions represented as OBDDs. Recent work in this area has focused on generalizations to represent larger classes of functions, as well as on scaling implementations to handle larger and more complex problems.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Akers, S.B.: Binary decision diagrams. IEEE Trans. Comput. C-27(6), 509–516 (1978) CrossRefGoogle Scholar
  2. 2.
    de Alfaro, L., Kwiatkowska, M., Parker, G.N.D., Segala, R.: Symbolic model checking of probabilistic processes using MTBDDs and the Kronecker representation. In: Graf, S., Schwartzbach, M. (eds.) Tools and Algorithms for the Construction and Analysis of Systems (TACAS). LNCS, vol. 1785, pp. 395–410. Springer, Heidelberg (2000) zbMATHGoogle Scholar
  3. 3.
    Aloul, F.A., Markov, I.L., Sakallah, K.A.: Faster SAT and smaller BDDs via common function structure. In: Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD), pp. 443–448. IEEE, Piscataway (2001) Google Scholar
  4. 4.
    Alur, R., Dill, D.: A theory of timed automata. Theor. Comput. Sci. 126(2), 183–235 (1994) MathSciNetCrossRefGoogle Scholar
  5. 5.
    Ashar, P., Cheong, M.: Efficient breadth-first manipulation of binary decision diagrams. In: Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD), pp. 622–627. IEEE, Piscataway (1994) Google Scholar
  6. 6.
    Aziz, A., Taşiran, S., Brayton, R.K.: BDD variable ordering for interacting finite state machines. In: Proc. of the 31st ACM/IEEE Design Automation Conf. (DAC), pp. 283–288. ACM/IEEE, New York/Piscataway (1994) Google Scholar
  7. 7.
    Bahar, R.I., Frohm, E.A., Gaona, C.M., Hachtel, G.D., Macii, E., Pardo, A., Somenzi, F.: Algebraic decision diagrams and their applications. In: Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD), pp. 188–191. IEEE, Piscataway (1993) Google Scholar
  8. 8.
    Barrett, C.W., Tinelli, C.: Satisfiability modulo theories. In: Clarke, E.M., Henzinger, T.A., Veith, H., Bloem, R. (eds.) Handbook of Model Checking. Springer, Heidelberg (2018) Google Scholar
  9. 9.
    Bollig, B., Wegener, I.: Improving the variable ordering of OBDDs is NP-complete. IEEE Trans. Comput. 45(9), 993–1002 (1996) CrossRefGoogle Scholar
  10. 10.
    Bose, S., Fisher, A.L.: Automatic verification of synchronous circuits using symbolic logic simulation and temporal logic. In: Claesen, L. (ed.) Proc. of the IMEC-IFIP Intl. Workshop on Applied Formal Methods for Correct VLSI Design, pp. 759–764 (1989) Google Scholar
  11. 11.
    Bouyer, P., Fahrenberg, U., Larsen, K.G., Markey, N., Ouaknine, J., Worrell, J.: Model checking real-time systems. In: Clarke, E.M., Henzinger, T.A., Veith, H., Bloem, R. (eds.) Handbook of Model Checking. Springer, Heidelberg (2018) Google Scholar
  12. 12.
    Brace, K.S., Rudell, R.L., Bryant, R.E.: Efficient implementation of a BDD package. In: Proc. of the 27th ACM/IEEE Design Automation Conf. (DAC), pp. 40–45. ACM/IEEE, New York/Piscataway (1990) CrossRefGoogle Scholar
  13. 13.
    Brayton, R.K., Hachtel, G.D., McMullen, C.T., Sangiovanni-Vincentelli, A.L.: Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic, Norwell (1984) CrossRefGoogle Scholar
  14. 14.
    Brown, F.M.: Boolean Reasoning. Kluwer Academic, Norwell (1990) CrossRefGoogle Scholar
  15. 15.
    Bryant, R.E.: Graph-based algorithms for Boolean function manipulation. IEEE Trans. Comput. C-35(8), 677–691 (1986) CrossRefGoogle Scholar
  16. 16.
    Bryant, R.E.: On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication. IEEE Trans. Comput. 40(2), 205–213 (1991) MathSciNetCrossRefGoogle Scholar
  17. 17.
    Bryant, R.E.: Symbolic Boolean manipulation with ordered binary decision diagrams. ACM Comput. Surv. 24(3), 293–318 (1992) MathSciNetCrossRefGoogle Scholar
  18. 18.
    Bryant, R.E.: Binary decision diagrams and beyond: Enabling technologies for formal verification. In: Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD), pp. 236–243. IEEE, Piscataway (1995) Google Scholar
  19. 19.
    Bryant, R.E.: A view from the engine room: Computational support for symbolic model checking. In: Grumberg, O., Veith, H. (eds.) 25 Years of Model Checking. LNCS, vol. 5000, pp. 145–149. Springer, Heidelberg (2008) CrossRefGoogle Scholar
  20. 20.
    Burch, J.R., Clarke, E.M., Long, D.E., McMillan, K.L.: Symbolic model checking for sequential circuit verification. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 13(4), 401–424 (1994) CrossRefGoogle Scholar
  21. 21.
    Burch, J.R., Clarke, E.M., McMillan, K.L., Dill, D.L., Hwang, L.J.: Symbolic model checking: \(10^{20}\) states and beyond. Inf. Comput. 98(2), 142–170 (1992) CrossRefGoogle Scholar
  22. 22.
    Chaki, S., Gurfinkel, A.: BDD-based symbolic model checking. In: Clarke, E.M., Henzinger, T.A., Veith, H., Bloem, R. (eds.) Handbook of Model Checking. Springer, Heidelberg (2018) zbMATHGoogle Scholar
  23. 23.
    Chaki, S., Gurfinkel, A., Strichman, O.: Decision diagrams for linear arithmetic. In: Biere, A., Pixley, C. (eds.) Formal Methods in Computer-Aided Design (FMCAD), pp. 53–60. IEEE, Piscataway (2009) Google Scholar
  24. 24.
    Ciardo, G., Marmorstein, R., Siminiceanu, R.: The saturation algorithm for symbolic state-space exploration. Int. J. Softw. Tools Technol. Transf. 8, 4–25 (2006) CrossRefGoogle Scholar
  25. 25.
    Coudert, O., Berthet, C., Madre, J.C.: Verification of synchronous sequential machines based on symbolic execution. In: Sifakis, J. (ed.) Proc. of the Workshop on Automatic Verification Methods for Finite State Systems. LNCS, vol. 407, pp. 365–373. Springer, Heidelberg (1989) CrossRefGoogle Scholar
  26. 26.
    Damiano, R., Kukula, J.: Checking satisfiability of a conjunction of BDDs. In: Proc. of the 40th ACM/IEEE Design Automation Conf. (DAC), pp. 818–923. ACM/IEEE, New York/Piscataway (2003) Google Scholar
  27. 27.
    Davis, M., Logemann, G., Loveland, D.: A machine program for theorem-proving. Commun. ACM 5(7), 394–397 (1962) MathSciNetCrossRefGoogle Scholar
  28. 28.
    Davis, M., Putnam, H.: A computing procedure for quantification theory. J. ACM 3, 201–215 (1960) MathSciNetCrossRefGoogle Scholar
  29. 29.
    van Dijk, T., Laarman, A.W., van de Pol, J.C.: Multi-core BDD operations for symbolic reachability. In: 11th Intl. Workshop on Parallel and Distributed Methods in Verification (PDMC) (2012) Google Scholar
  30. 30.
    Drechsler, R., Günther, W., Somenzi, F.: Using lower bounds during dynamic BDD minimization. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 20(1), 51–57 (2001) CrossRefGoogle Scholar
  31. 31.
    Drechsler, R., Sieling, D.: Binary decision diagrams in theory and practice. Int. J. Softw. Tools Technol. Transf. 3(2), 112–136 (2001) zbMATHGoogle Scholar
  32. 32.
    Friedman, S.J., Supowit, K.J.: Finding the optimum variable ordering for binary decision diagrams. IEEE Trans. Comput. 39(5), 710–713 (1990) MathSciNetCrossRefGoogle Scholar
  33. 33.
    Fujita, M., Fujisawa, H., Kawato, N.: Evaluation and improvements of Boolean comparison method based on binary decision diagrams. In: Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD), pp. 2–5. IEEE, Piscataway (1988) Google Scholar
  34. 34.
    Fujita, M., McGeer, P.C., Yang, J.C.: Multi-terminal binary decision diagrams: an efficient data structure for matrix representation. Form. Methods Syst. Des. 10, 149–169 (1997) CrossRefGoogle Scholar
  35. 35.
    Garey, M.R., Johnson, D.S.: Computers and Intractability. Freeman, New York (1979) zbMATHGoogle Scholar
  36. 36.
    Gunther, W., Drechsler, R.: Minimization of free BDDs. In: Proc. of the 1999 Conf. on Asia South Pacific Design Automation (ASP-DAC), pp. 323–326. IEEE, Piscataway (1999) Google Scholar
  37. 37.
    Heyman, T., Geist, D., Grumberg, O., Shuster, A.: Achieving scalability in parallel reachability analysis of very large circuits. In: Emerson, E.A., Sistla, A.P. (eds.) Proc. of the 12th Intl. Conf. of Computer Aided Verification (CAV). LNCS, vol. 1855, pp. 20–35. Springer, Heidelberg (2000) CrossRefGoogle Scholar
  38. 38.
    Huang, J., Darwiche, A.: Using DPLL for efficient OBDD construction. In: Hoos, H.H., Mitchell, D.G. (eds.) Theory and Applications of Satisfiability Testing (SAT). LNCS, vol. 3542, pp. 157–172. Springer, Heidelberg (2005) CrossRefGoogle Scholar
  39. 39.
    Jeong, S.W., Plessier, B., Hachtel, G.D., Somenzi, F.: Variable ordering and selection of FSM traversal. In: Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD). IEEE, Piscataway (1991) Google Scholar
  40. 40.
    Kam, T., Villa, T., Brayton, R.K., Sangiovanni-Vincentelli, A.L.: Multi-valued decision diagrams: theory and applications. Mult. Valued Log. 4(1–2), 9–62 (1998) MathSciNetzbMATHGoogle Scholar
  41. 41.
    Knuth, D.S.: The Art of Computer Programming, vol. 4: Combinatorial Algorithms. Addison-Wesley, Reading (2011) Google Scholar
  42. 42.
    Kunkle, D., Slavici, V., Cooperman, G.: Parallel disk-based computation for large, monolithic binary decision diagrams. In: Maza, M.M., Roch, J.-L. (eds.) Proc. of the 4th Intl. Workshop on Parallel and Symbolic Computation (PASCO), pp. 63–72. ACM, New York (2010) CrossRefGoogle Scholar
  43. 43.
    Kwiatkowska, M., Norman, G., Parker, D.P.: Probabilistic symbolic model checker. In: Field, T., Harrison, P.G., Bradley, J., Harder, U. (eds.) Computer Performance Evaluation: Modelling Techniques and Tools (TOOLS). LNCS, vol. 2324, pp. 113–140. Springer, Heidelberg (2002) Google Scholar
  44. 44.
    Larsen, K.G., Pearson, J., Weise, C., Yi, W.: Clock difference diagrams. Nord. J. Comput. 6(3), 271–298 (1999) MathSciNetzbMATHGoogle Scholar
  45. 45.
    Madre, J.C., Billon, J.P.: Proving circuit correctness using formal comparison between expected and extracted behaviour. In: Proc. of the 25th ACM/IEEE Design Automation Conf. (DAC), pp. 205–210. ACM/IEEE, New York/Piscataway (1988) Google Scholar
  46. 46.
    Malik, S., Wang, A., Brayton, R.K., Sangiovanni-Vincentelli, A.L.: Logic verification using binary decision diagrams in a logic synthesis environment. In: Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD), pp. 6–9. IEEE, Piscataway (1988) Google Scholar
  47. 47.
    Marques-Silva, J., Malik, S.: Propositional SAT solving. In: Clarke, E.M., Henzinger, T.A., Veith, H., Bloem, R. (eds.) Handbook of Model Checking. Springer, Heidelberg (2018) Google Scholar
  48. 48.
    McDonald, C.B., Bryant, R.E.: CMOS circuit verification with symbolic switch-level timing simulation. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 20(3), 458–474 (2001) CrossRefGoogle Scholar
  49. 49.
    McMillan, K.L.: Symbolic Model Checking. Kluwer Academic, Norwell (1993) CrossRefGoogle Scholar
  50. 50.
    Michie, D.: “Memo” functions and machine learning. Nature 218, 19–22 (1968) CrossRefGoogle Scholar
  51. 51.
    Minato, S.: Zero-suppressed BDDs for set manipulation in combinatorial problems. In: Proc. of the 30th ACM/IEEE Design Automation Conf. (DAC), pp. 272–277. ACM/IEEE, New York/Piscataway (1993) CrossRefGoogle Scholar
  52. 52.
    Minato, S., Ishiura, N., Yajima, S.: Shared binary decision diagrams with attributed edges for efficient Boolean function manipulation. In: Proc. of the 27th ACM/IEEE Design Automation Conf. (DAC), pp. 52–57. ACM/IEEE, New York/Piscataway (1990) CrossRefGoogle Scholar
  53. 53.
    Møller, J., Lichtenberg, J., Andersen, H., Hulgaard, H.: Difference decision diagrams. In: Flum, J., Rodriguez-Artalejo, M. (eds.) Computer Science Logic (CSL). LNCS, vol. 1683, p. 826. Springer, Heidelberg (1999) Google Scholar
  54. 54.
    Narayan, A., Jain, J., Fujita, M., Sangiovanni-Vincentelli, A.L.: Partitioned OBDDs—a compact, canonical, and efficiently manipulable representation for Boolean functions. In: Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD), pp. 547–554. IEEE, Piscataway (1996) CrossRefGoogle Scholar
  55. 55.
    Ochi, H., Yasuoka, K., Yajima, S.: Breadth-first manipulation of very large binary-decision diagrams. In: Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD), pp. 48–55. IEEE, Piscataway (1993) Google Scholar
  56. 56.
    Ossowski, J.: JINC—a multi-threaded library for higher-order weighted decision diagram manipulation. Ph.D. thesis, Rheinische Friedrich-Wilhelms-Universität, Bonn (2009) Google Scholar
  57. 57.
    Panda, S., Somenzi, F.: Who are the variables in your neighbourhood. In: Formal Methods in Computer-Aided Design (FMCAD), pp. 74–77. IEEE, Piscataway (1995) Google Scholar
  58. 58.
    Ranjan, R.K., Sanghavi, J.V., Brayton, R.K., Sangiovanni-Vincentelli, A.L.: High performance BDD package based on exploiting memory hierarchy. In: Proc. of the 33rd ACM/IEEE Design Automation Conf. (DAC), pp. 635–640. ACM/IEEE, New York/Piscataway (1996) Google Scholar
  59. 59.
    Rudell, R.L.: Dynamic variable ordering for ordered binary decision diagrams. In: Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD), pp. 139–144. IEEE, Piscataway (1993) Google Scholar
  60. 60.
    Schröer, O., Wegener, I.: The theory of zero-suppressed BDDs and the number of knight’s tours. Form. Methods Syst. Des. 13(3), 235–253 (1998) CrossRefGoogle Scholar
  61. 61.
    Sieling, D.: On the existence of polynomial time approximation schemes for OBDD minimization. In: Morvan, M., Meinel, C., Krob, D. (eds.) Symp. on Theoretical Aspects of Computer Science (STACS). LNCS, vol. 1373, pp. 205–215. Springer, Heidelberg (1998) Google Scholar
  62. 62.
    Sieling, D., Wegener, I.: Reduction of OBDDs in linear time. Inf. Process. Lett. 48(3), 139–144 (1993) MathSciNetCrossRefGoogle Scholar
  63. 63.
    Somenzi, F.: Efficient manipulation of decision diagrams. Int. J. Softw. Tools Technol. Transf. 3(2), 171–181 (2001) zbMATHGoogle Scholar
  64. 64.
    Stornetta, T., Brewer, F.: Implementation of an efficient parallel BDD package. In: Proc. of the 33rd ACM/IEEE Design Automation Conf. (DAC), pp. 641–644. ACM/IEEE, New York/Piscataway (1996) Google Scholar
  65. 65.
    Tani, S., Hamaguchi, K., Yajima, S.: The complexity of the optimal variable ordering problems of shared binary decision diagrams. Algorithms Comput. 762, 389–398 (1993) MathSciNetzbMATHGoogle Scholar
  66. 66.
    Wang, F.: Efficient verification of timed automata with efficient BDD-like data structures. Int. J. Softw. Tools Technol. Transf. 6(1), 77–97 (2004) CrossRefGoogle Scholar
  67. 67.
    Yang, B., Bryant, R.E., O’Hallaron, D.R., Biere, A., Coudert, O., Janssen, G., Ranjan, R.K., Somenzi, F.: A performance study of BDD-based model checking. In: Gopalakrishnan, G., Windley, P. (eds.) Formal Methods in Computer-Aided Design (FMCAD). LNCS, vol. 1522. Springer, Heidelberg (1998) Google Scholar
  68. 68.
    Yang, B., Chen, Y.A., Bryant, R.E., O’Hallaron, D.R.: Space- and time-efficient BDD construction via working set control. In: Proc. of the 1998 Conf. on Asia South Pacific Design Automation (ASP-DAC), pp. 423–432. IEEE, Piscataway (1998) CrossRefGoogle Scholar
  69. 69.
    Yoneda, T., Hatori, H., Takahara, A., Minato, S.: BDDs vs. zero-suppressed BDDs for CTL symbolic model checking of Petri nets. In: Srivas, M., Camilleri, A. (eds.) Formal Methods in Computer-Aided Design (FMCAD). LNCS, vol. 1166, pp. 435–449. Springer, Heidelberg (1996) CrossRefGoogle Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Carnegie Mellon UniversityPittsburghUSA

Personalised recommendations