Skip to main content
SpringerLink
Log in

Theoretical Study of Continuous-Time Equalizers

  • Chapter
  • First Online:
Book cover CMOS Continuous-Time Adaptive Equalizers for High-Speed Serial Links

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

Abstract

In this chapter, the principles of continuous-time adaptive equalization will be explored. First, basic theory of continuous-time equalization will be analyzed, focusing on its transfer function and how it should compensate the response of the channel. Second, the power spectrum characteristics of the transferred data will be analyzed, focusing on the non-return-to-zero (NRZ) data encoding and pseudo random bit sequence (PRBS) , which is the typical signal used to test serial communication prototypes. Next, a thorough and unified analysis of continuous-time adaptive equalizers that will lead to a set of design criteria to select the proper bandwidth of the filters used in the adaptation loop will be presented. It has into account the characteristics of the communications system such as the data rate, channel bandwidth and the specific line equalizer used. After this analysis, a functional simulation of continuous-time adaptive equalizers will be presented to determine which filters are preferred in the adaptation loop . Finally, some conclusions of the chapter will be drawn.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 99.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 129.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 139.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    The transition time is defined as the time taken by the signal to change from a specified low value to a specified high value or vice versa. In our case, these values are 10 and 90 % of the step height.

  2. 2.

    Variance: Difference between the maximum and minimum value in the stationary state.

References

  1. W. Beyene, The design of continuous-time linear equalizers using model order reduction techniques, in Proceedings of IEEE Electrical Performance of Electronic Packaging (IEEE-EPEP), pp. 187–190, Oct 2008

    Google Scholar 

  2. W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, Y.-Z. Juang, A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer, in IEEE Asian Solid-State Circuits Conference 2007 (ASSCC’07), pp. 396–399, Nov 2007

    Google Scholar 

  3. K.-H. Cheng, Y.-C. Tsai, Y.-H. Wu, Y.-F. Lin, A 5-Gb/s Inductorless CMOS adaptive equalizer for pci express generation II applications. IEEE Trans. Circuits Syst. II Express Briefs 57(5), 324–328 (2010)

    Article  Google Scholar 

  4. A.A. Fayed, M. Ismail, A low-voltage low-power CMOS analog adaptive equalizer for UTP-5 cables. IEEE Trans. Circuits Syst. I Regul. Pap. 55(2), 480–495 (2008)

    Article  MathSciNet  Google Scholar 

  5. C. Gimeno, E. Guerrero, C. Aldea, S. Celma, A 2.5 Gb/s low-voltage CMOS fully-differential adaptive equalizer, in Proceedings of 2013 SPIE Microtechnologies Conference (SPIE 2013), pp. 876402-1–876402-8, Apr 2013

    Google Scholar 

  6. C. Gimeno, C. Sánchez-Azqueta, E. Guerrero, C. Aldea, S. Celma, A 1-V 1.25-Gbps CMOS analog front-end for short reach optical links, in IEEE European Solid-State Circuits Conference (ESSCIRC2013), pp. 339–342, Sept 2013

    Google Scholar 

  7. S. Gondi, B. Razavi, Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-link receivers. IEEE J. Solid-State Circuits 42(9), 1999–2011 (2007)

    Article  Google Scholar 

  8. J.W. Goodman, Statistical optics (Wiley, New York, 1985)

    Google Scholar 

  9. G. Hartman, K. Martin, A. McLaren, Continuous-time adaptive analog coaxial cable equalizer in 0.5 µm CMOS, in Proceedings of the 1999 IEEE International Symposium on Circuits and Systems (ISCAS99), pp. 97–100, Jul 1999

    Google Scholar 

  10. S. Haykin, Communication Systems, 4th edn (Wiley, New York, 2001)

    Google Scholar 

  11. T. Hollis, D. Comer, Mitigating ISI through selfcalibrating continuous-time equalization. IEEE Trans. Circuits Syst. I Regul. Pap. 53(10), 2234–2245 (2006)

    Article  Google Scholar 

  12. D. Hong, S. Saberi, K.-T. Cheng, C. P. Yue, A two-tone test method for continuous-time adaptive equalizers, in Efficient Test Methodologies for High-Speed Serial Links (Springer, Berlin, 2010), pp. 75–87

    Google Scholar 

  13. L. Hoon, H. Gunhee, A low power and small area analog adaptive line equalizer for 100 Mb/s data rate on UTP cable. IEICE Trans. Electron. 87(4), 634–639 (2004)

    Google Scholar 

  14. J. Lee, A 20-Gb/s adaptive equalizer in 0.13-µm CMOS technology. IEEE J. Solid-State Circuits 41(9), 2058–2066 (2006)

    Article  Google Scholar 

  15. D. Lee, J. Han, G. Han, S.M. Park, 10 Gbit/s 0.0065 mm2 6 mW analogue adaptive equalizer utilising negative capacitance, in IEEE International Solid-State Circuits Conference (ISSCC), pp. 190–191, Feb 2009

    Google Scholar 

  16. Maxim Integrated Products, 3.2 Gbps Equalizer and Cable Driver (2005)

    Google Scholar 

  17. C. Sánchez-Azqueta, S. Celma, A phase detection scheme for clock and data recovery applications, in Proceedings of the 20th IEEE European Conference on Circuit Theory and Design (ECCTD2011), pp. 130–133, Aug 2011

    Google Scholar 

  18. C. Sánchez-Azqueta, C. Gimeno, S. Celma, A comparative study of continuous-time analog adaptive equalizers, in Proceedings of the 2013 SPIE Microtechnologies Conference (SPIE 2013), vol. 8764, pp. 876402-8, Apr 2013

    Google Scholar 

  19. C. Sánchez-Azqueta, C. Gimeno, E. Guerrero, C. Aldea, S. Celma, Design considerations for loop filters in continuous-time adaptive equalizers, in Proceedings of the International Multi-Conference on Systems, Signals and Devices (SSD 2014), Feb 2014

    Google Scholar 

  20. D.H. Shin, J.E. Jang, F. O’Mahony, C.P. Yue, A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS, in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC09), pp. 117–120, Sept 2009

    Google Scholar 

  21. R. Sun, A low-power 20-Gb/s continuous-time adaptive passive equalizer. Thesis, B.S. Tsinghua University 1999, Dec 2005

    Google Scholar 

  22. K. Yoo, G. Han, H. Yoon, Convergence analysis of the cascade second-order adaptive line equalizer. IEEE Trans. Circuits Syst. II Express Briefs 53(6), 507–511 (2006)

    Article  Google Scholar 

  23. G.E. Zhang, M.M. Green, A 10 Gb/s BiCMOS adaptive cable equalizer. IEEE J. Solid-State Circuits 40(11), 2132–2140 (2005)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Faculty of Sciences, Electronics Area, University of Zaragoza, Zaragoza, Spain

    Cecilia Gimeno Gasca, Santiago Celma Pueyo & Concepción Aldea Chagoyen

Authors
  1. Cecilia Gimeno Gasca
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Santiago Celma Pueyo
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Concepción Aldea Chagoyen
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Cecilia Gimeno Gasca .

Rights and permissions

Reprints and permissions

Copyright information

© 2015 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Gimeno Gasca, C., Celma Pueyo, S., Aldea Chagoyen, C. (2015). Theoretical Study of Continuous-Time Equalizers. In: CMOS Continuous-Time Adaptive Equalizers for High-Speed Serial Links. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-10563-5_2

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-10563-5_2

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-10562-8

  • Online ISBN: 978-3-319-10563-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation