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Aligned Scheduling: Cache-Efficient Instruction Scheduling for VLIW Processors

  • Vasileios Porpodas
  • Marcelo Cintra
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8664)

Abstract

The performance of statically scheduled VLIW processors is highly sensitive to the instruction scheduling performed by the compiler. In this work we identify a major deficiency in existing instruction scheduling for VLIW processors. Unlike most dynamically scheduled processors, a VLIW processor with no load-use hardware interlocks will completely stall upon a cache-miss of any of the operations that are scheduled to run in parallel. Other operations in the same or subsequent instruction words must stall. However, if coupled with non-blocking caches, the VLIW processor is capable of simultaneously resolving multiple loads from the same word. Existing instruction scheduling algorithms do not optimize for this VLIW-specific problem.

We propose Aligned Scheduling, a novel instruction scheduling algorithm that improves performance of VLIW processors with non-blocking caches by enabling them to better cope with unpredictable cache-memory latencies. Aligned Scheduling exploits the VLIW-specific cache-miss semantics to efficiently align cache misses on the same scheduling cycle, increasing the probability that they get serviced simultaneously. Our evaluation shows that Aligned Scheduling improves the performance of VLIW processors across a range of benchmarks from the Mediabench II and SPEC CINT2000 benchmark suites up to 20 %.

Keywords

Schedule Algorithm Cache Size Current Cycle Load Instruction Instruction Schedule 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Gcc: Gnu compiler collection. http://gcc.gnu.org
  2. 2.
    ski IA64 simulator. http://ski.sourceforge.net
  3. 3.
    SPEC benchmark. http://www.spec.org
  4. 4.
    Branover, A., et al.: AMD Fusion APU: Llano. IEEE Micro 32(2), 28–37 (2012)CrossRefGoogle Scholar
  5. 5.
    Dehnert, J., et al.: The Transmeta code morphing software: using speculation, recovery, and adaptive retranslation to address real-life challenges. In: CGO (2003)Google Scholar
  6. 6.
    Dehnert, J., et al.: Compiling for the Cydra. J. Supercomput. 7, 181–227 (1993)CrossRefGoogle Scholar
  7. 7.
    Ding, C., Carr, S., Sweany, P.: Modulo scheduling with cache reuse information. In: Lengauer, C., Griebl, M., Gorlatch, S. (eds.) Euro-Par 1997. LNCS, vol. 1300, pp. 1079–1083. Springer, Heidelberg (1997) CrossRefGoogle Scholar
  8. 8.
    Faraboschi, P., et al.: Lx: a technology platform for customizable VLIW embedded processing. In: ISCA (2000)Google Scholar
  9. 9.
    Fisher, J.: Trace scheduling: a technique for global microcode compaction. IEEE Trans. Comput. 30(7), 478–490 (1981)CrossRefGoogle Scholar
  10. 10.
    Fisher, J.A., Faraboschi, P., Young, C.: VLIW processors. In: Padua, D. (ed.) Encyclopedia of Parallel Computing, pp. 2135–2142. Springer, Heidelberg (2011)Google Scholar
  11. 11.
    Fridman, J., Greenfield, Z.: The TigerSHARC DSP architecture. IEEE Micro 20(1), 66–176 (2000)CrossRefGoogle Scholar
  12. 12.
    Fritts, J., et al.: Mediabench II video: expediting the next generation of video systems research. In: SPIE (2005)Google Scholar
  13. 13.
    Kerns, D., Eggers, S.: Balanced scheduling: instruction scheduling when memory latency is uncertain. In: PLDI (1993)Google Scholar
  14. 14.
    Klaiber, A., et al.: The technology behind Crusoe processors. Transmeta Corporation White Paper (2000)Google Scholar
  15. 15.
    Kroft, D.: Lockup-free instruction fetch/prefetch cache organization. In: ISCA (1981)Google Scholar
  16. 16.
    Lam, M.: Software pipelining: an effective scheduling technique for VLIW machines. In: PLDI (1988)Google Scholar
  17. 17.
    Lindenmaier, G., McKinley, K.S., Temam, O.: Load scheduling with profile information. In: Bode, A., Ludwig, T., Karl, W.C., Wismüller, R. (eds.) Euro-Par 2000. LNCS, vol. 1900, pp. 223–233. Springer, Heidelberg (2000) CrossRefGoogle Scholar
  18. 18.
    Llosa, J.: Swing modulo scheduling: a lifetime-sensitive approach. In: PACT (1996)Google Scholar
  19. 19.
    Lo, J., et al.: Improving balanced scheduling with compiler optimizations that increase instruction-level parallelism. In: PLDI (1995)Google Scholar
  20. 20.
    McNairy, C., et al.: Itanium 2 processor microarchitecture. IEEE Micro 23(2), 44–55 (2003)CrossRefGoogle Scholar
  21. 21.
    Moon, S., et al.: An efficient resource-constrained global scheduling technique for superscalar and VLIW processors. In: MICRO (1992)Google Scholar
  22. 22.
    Pai, V., et al.: Code transformations to improve memory parallelism. In: MICRO (1999)Google Scholar
  23. 23.
    Pechanek, G., Vassiliadis, S.: The ManArrayTM embedded processor architecture. In: Euromicro (2000)Google Scholar
  24. 24.
    Rau, B., Glaeser, C.: Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. In: Workshop on Microprogramming (1981)Google Scholar
  25. 25.
    Sánchez, F., González, A.: Cache sensitive modulo scheduling. In: MICRO (1997)Google Scholar
  26. 26.
    Scheurich, C., et al.: Lockup-free caches in high-performance multiprocessors. J. Parallel Distrib. Syst. 11(1), 25–36 (1991)CrossRefGoogle Scholar
  27. 27.
    Sharangpanim, H., et al.: Itanium processor microarchitecture. IEEE Micro 20(5), 24–43 (2000)CrossRefGoogle Scholar
  28. 28.
    Sohi, G., Franklin, M.: High-bandwidth data memory systems for superscalar processors. In: ASPLOS (1991)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  1. 1.School of InformaticsUniversity of EdinburghEdinburghUK
  2. 2.Intel Labs BraunschweigBraunschweigGermany

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