Abstract
This chapter addresses some of the practical difficulties when designing a silicon-PUF based on CMOS technology. When designing such a PUF, and particularly in the case of an arbiter-PUF, particular care should be taken during the place and route phase. To ensure the properties of the PUF, full-custom back-end design may be required. This chapter give details on the design phase considering the example of an arbiter-PUF made of several switch boxes. Each of them can be configured by the challenge, and an arbiter (NAND2 – RS-latch) to decide of the output of the PUF. The technology node targeted for the ASIC implementation is the CMOS 65 nm.
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References
Gassend, B., Clarke, D., Van Dijk, M., Devadas, S.: Silicon physical random functions. In: Proceedings of the 9th ACM Conference on Computer and Communications Security, Washington, DC, pp. 148–160. ACM (2002)
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© 2015 Springer International Publishing Switzerland
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Reymond, G., Fournier, J.J.A. (2015). Physically Unclonable Function: Design of a Silicon Arbiter-PUF on CMOS 65nm. In: Candaele, B., Soudris, D., Anagnostopoulos, I. (eds) Trusted Computing for Embedded Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-09420-5_7
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DOI: https://doi.org/10.1007/978-3-319-09420-5_7
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