Abstract
Each combinational circuit is represented by a directed acyclic graph C = (V, E), referred to as the circuit graph, where V is the set of circuit nodes and E ⊆ V × V, the set of edges, corresponds to the gate input-output connections in the circuit [LRS89]. For gate-level benchmarks, we consider the nodes to be gates with symmetric functions. Each node in the circuit graph is associated with a symmetric function which represents the corresponding behavior of that gate in the circuit. A symmetric function does not depend on the order of inputs but only on the sum of variables assigned to 0 or to 1, respectively.
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References
Robert C Aitken. Modeling the unmodelable: Algorithmic fault diagnosis. IEEE Design & Test of Computers, 14(3):98–103, 1997.
Franc Brglez, David Bryan, and Krzysztof Kozminski. Combinational profiles of sequential benchmark circuits. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 1929–1934, 1989.
Franc Brglez, Phillip Pownall, and Robert Hum. Accelerated ATPG and fault grading via testability analysis. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 695–698, 1985.
Franc Brglez. A fast fault grader: Analysis and applications. In Proceedings of the International Test Conference, pages 785–794, 1985.
S. Davidson. ITC99 Benchmark. http://www.cerc.utexas.edu/itc99-benchmarks/bench.html [accessed: 2014-05-20], 1999.
Johan de Kleer and James Kurien. Fundamentals of model-based diagnosis. In IFAC Symposium on Fault Detection, Supervision, and Safety of Technical Processes, pages 25–36, 2003.
Goerschwin Fey and Rolf Drechsler. Efficient hierarchical system debugging for property checking. In In IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2005, pages 41–46, 2005.
Goerschwin Fey, Stefan Staber, Roderick Bloem, and Rolf Drechsler. Automatic fault localization for property checking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(6):1138–1149, 2008.
Gerhard Friedrich, Markus Stumptner, and Franz Wotawa. Model-based diagnosis of hardware designs. Artificial Intelligence, 111(1–2):3–39, 1999.
Amir Masoud Gharehbaghi and Masahiro Fujita. Transaction-based debugging of system-on-chips with patterns. In International Conference on Computer Design, pages 186–192, 2009.
Alex Groce and Daniel Kroening. Making the most of BMC counterexamples. Electronic Notes in Theoretical Computer Science, 119(2):67–81, 2005.
Aarti Gupta. SAT-based scalable formal verification solutions. Springer, 2007.
Kees Goossens, Bart Vermeulen, Remco Van Steeden, and Martijn Bennebroek. Transaction-based communication-centric debug. In International Symposium on Networks-on-Chips, pages 95–106, 2007.
IEEE. IEEE Std 1850–2005 – IEEE Standard for Property Specification Language (PSL). The IEEE, 2005.
L. Jain. NIRGAM: A Simulator for NoC Interconnect Routing and Application Modeling – Version 1.1, 2007. http://nirgam.ecs.soton.ac.uk/ [accessed: 2014-05-20].
Tracy Larrabee. Test pattern generation using boolean satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(1): 4–15, 1992.
Damjan Lampret and Julius Baxter. OpenRISC 1200 IP Core Specification (Preliminary Draft), 2014. http://www.openrisc.net [accessed: 2014-05-20].
Wing-Ning Li, Sudhakar M Reddy, and Sartaj K Sahni. On path selection in combinational logic circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(1):56–63, 1989.
Jiang Brandon Liu and Andreas Veneris. Incremental fault diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(2): 240–251, 2005.
K. McElvain. IWLS’93 Benchmark Set: Version 4.0. http://www.cbl.ncsu.edu/benchmarks/LGSynth93 [accessed: 2014-05-20], 1993.
Joao Marques-Silva. Search algorithms for satisfiability problems in combinational switching circuits. PhD thesis, University of Michigan, 1995.
Wolfgang Mayer and Markus Stumptner. Model-based debugging–state of the art and future challenges. Electronic Notes in Theoretical Computer Science, 174(4): 61–82, 2007.
Nangate. Nangate 45nm Open Cell Library, 2011. http://www.nangate.com [accessed: 2014-05-20].
Open SystemC Initiative. TLM-2.0 Language Reference Manual, 2009. http://www.systemc.org [accessed: 2014-05-20].
Raymond Reiter. A theory of diagnosis from first principles. Artificial Intelligence, 32:57–95, 1987.
Kavita Ravi and Fabio Somenzi. Minimal assignments for bounded model checking. In Tools and Algorithms for the Construction and Analysis of Systems, volume 2988 of LNCS, pages 31–45, 2004.
Alexander Smith, Andreas Veneris, Moayad Fahim Ali, and Anastasios Viglas. Fault diagnosis and logic debugging using Boolean satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(10):1606–1621, 2005.
Sean Safarpour, Andreas G Veneris, and Rolf Drechsler. Improved SAT-based reachability analysis with observability don’t cares. Journal of Satisfiability, Boolean Modeling and Computation, 5:1–25, 2008.
Grigori S Tseitin. On the complexity of derivation in the propositional calculus. Zapiski nauchnykh seminarov LOMI, 8:234–259, 1968.
Miroslav N Velev. Comparison of schemes for encoding unobservability in translation to SAT. In Proceedings of the ASP Design Automation Conference, pages 1056–1059, 2005.
Andreas Veneris and Ibrahim N Hajj. Design error diagnosis and correction via test vector simulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(12):1803–1816, 1999.
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Dehbashi, M., Fey, G. (2015). Preliminaries. In: Debug Automation from Pre-Silicon to Post-Silicon. Springer, Cham. https://doi.org/10.1007/978-3-319-09309-3_2
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