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Microcode Verification – Another Piece of the Microprocessor Verification Puzzle

  • Conference paper

Part of the Lecture Notes in Computer Science book series (LNTCS,volume 8558)

Abstract

Despite significant progress in formal hardware verification in the past decade, little has been published on the verification of microcode. Microcode is the heart of every microprocessor and is one of the most complex parts of the design: it is tightly connected to the huge machine state, written in an assembly-like language that has no support for data or control structures, and has little documentation and changing semantics. At the same time it plays a crucial role in the way the processor works.

We describe the method of formal microcode verification we have developed for an x86-64 microprocessor designed at Centaur Technology. While the previous work on high and low level code verification is based on an unverified abstract machine model, our approach is tightly connected with our effort to verify the register-transfer level implementation of the hardware. The same microoperation specifications developed to verify implementation of teh execution units are used to define operational semantics for the microcode verification.

While the techniques used in the described verification effort are not inherently new, to our knowledge, our effort is the first interconnection of hardware and microcode verification in context of an industrial size design. Both our hardware and microcode verifications are done within the same verification framework.

Keywords

  • Operational Semantic
  • Block Cipher
  • Symbolic Execution
  • Program Counter
  • Execution Unit

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. Hunt Jr., W.A., Swords, S.: Centaur Technology media unit verification. In: Bouajjani, A., Maler, O. (eds.) CAV 2009. LNCS, vol. 5643, pp. 353–367. Springer, Heidelberg (2009)

    CrossRef  Google Scholar 

  2. Hunt Jr., W.A., Swords, S., Davis, J., Slobodova, A.: Use of Formal Verification at Centaur Technology. In: Hardin, D. (ed.) Design and Verification of Microprocessor Systems for High-Assurance Applications, pp. 65–88. Springer (2010)

    Google Scholar 

  3. Slobodova, A., Davis, J., Swords, S., Hunt Jr., W.: A flexible formal verification framework for industrial scale validation. In: Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE), Cambridge, UK, pp. 89–97. IEEE/ACM (July 2011)

    Google Scholar 

  4. Kaufmann, M., Moore, J.S., Boyer, R.S.: ACL2 version 6.1 (2013), http://www.cs.utexas.edu/~moore/acl2/

  5. Ray, S., Moore, J.S.: Proof styles in operational semantics. In: Hu, A.J., Martin, A.K. (eds.) FMCAD 2004. LNCS, vol. 3312, pp. 67–81. Springer, Heidelberg (2004)

    CrossRef  Google Scholar 

  6. Moore, J.S.: Proving theorems about Java and the JVM with ACL2. In: Models, Algebras and Logic of Engineering Software, pp. 227–290 (2003)

    Google Scholar 

  7. Hardin, D.S., Smith, E.W., Young, W.D.: A robust machine code proof framework for highly secure applications. In: Proceedings of the Sixth International Workshop on the ACL2 Theorem Prover and its Applications, pp. 11–20. ACM (2006)

    Google Scholar 

  8. Swords, S., Davis, J.: Bit-blasting ACL2 theorems. In: ACL2 2011. Electronic Proceedings in Theoretical Computer Science, vol. 70, pp. 84–102 (2011)

    Google Scholar 

  9. Davis, J., Swords, S.: Verified AIG algorithms in ACL2. In: Proceedings of ACL2 Workshop (2013)

    Google Scholar 

  10. McCarthy, J.: Towards a mathematical Scioence of computation. In: Information Processing Congress, vol. 62, pp. 21–28. North-Holland (1962)

    Google Scholar 

  11. van Wijngaarden, A., Mailloux, B., Peck, J., Koster, C., Sintzoff, M., Lindsey, C., Meertens, L., Fisker, R.G.: Revised report on the algorithmic language ALGOL 68 (1968)

    Google Scholar 

  12. Boyer, R., Moore, J.: Mechanized formal reasoning about programs and computing machines. In: Automated Reasoning and its Applications: Essays in Honor of Larry Woss, pp. 141–176 (1996)

    Google Scholar 

  13. Greeve, D., Wilding, M., Hardin, D.: High-speed, analyzable simulators. In: Kaufmann, M., Moore, J.S., Manolios, P. (eds.) Computer-Aided Reasoning: ACL2 Case Studies, pp. 89–106. Kluwer Academic Publishers (2000)

    Google Scholar 

  14. Yu, Y.: Automated proofs of object code for a widely used microprocessor. PhD. Thesis (1992)

    Google Scholar 

  15. Strecker, M.: Formal verification of a Java compiler in Isabelle. In: Voronkov, A. (ed.) CADE 2002. LNCS (LNAI), vol. 2392, pp. 63–77. Springer, Heidelberg (2002)

    CrossRef  Google Scholar 

  16. Hamon, G., Rushby, J.: An operational semantics for stateflow. In: Wermelinger, M., Margaria-Steffen, T. (eds.) FASE 2004. LNCS, vol. 2984, pp. 229–243. Springer, Heidelberg (2004)

    CrossRef  Google Scholar 

  17. Smith, E., Dill, D.: Automatic formal verification of Block Cipher implementations. In: Cimatti, A., Jones, R. (eds.) Proceedings of the Conference on Formal Methods in Computer-Aided Design (FMCAD), pp. 45–51. IEEE/ACM (2008)

    Google Scholar 

  18. Goel, S., Hunt Jr., W.A.: Automated code proofs on a formal model of the X86. In: Cohen, E., Rybalchenko, A. (eds.) VSTTE 2013. LNCS, vol. 8164, pp. 222–241. Springer, Heidelberg (2013)

    CrossRef  Google Scholar 

  19. Fox, A., Myreen, M.O.: A trustworthy monadic formalization of the ARMv7 instruction set architecture. In: Kaufmann, M., Paulson, L.C. (eds.) ITP 2010. LNCS, vol. 6172, pp. 243–258. Springer, Heidelberg (2010)

    CrossRef  Google Scholar 

  20. Wilding, M., Greeve, D., Richards, R., Hardin, D.: Formal verification of partition management of the AAMP7G microprocessor. In: Hardin, D. (ed.) Design and Verification of Microprocessor Systems for High-Assurance Applications, pp. 175–192. Springer (2010)

    Google Scholar 

  21. Cyrluk, D.: Microprocessor verification in pvs. A methodology and simple example. (February 1994), http://www.csl.sri.com/papers/csl-93-12/

  22. Sawada, J., Hunt Jr., W.: Verification of FM9801: An out-of-order microprocessor model with speculative execution, exceptions, and program-modifying capability. J. of Formal Methods in System Design 20(2), 187–222 (2002)

    CrossRef  MATH  Google Scholar 

  23. Hunt Jr., W.A.: FM8501: A Verified Microprocessor. LNCS, vol. 795. Springer, Heidelberg (1994)

    MATH  Google Scholar 

  24. Arons, T., Elster, E., Fix, L., Mador-Haim, S., Mishaeli, M., Shalev, J., Singerman, E., Tiemeyer, A., Vardi, M.Y., Zuck, L.D.: Formal verification of backward compatibility of microcode. In: Etessami, K., Rajamani, S.K. (eds.) CAV 2005. LNCS, vol. 3576, pp. 185–198. Springer, Heidelberg (2005)

    CrossRef  Google Scholar 

  25. Franzén, A., Cimatti, A., Nadel, A., Sebastiani, R., Shalev, J.: Applying SMT in symbolic execution of microcode. In: Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design (FMCAD), Austin, TX, pp. 121–128, FMCAD Inc (2010)

    Google Scholar 

  26. Floyd, R.: Assigning meanings to programs. In: Mathematical Aspects of Computer Science, Proceeings of Symposia in Applied Mathematics, vol. XIX, pp. 19–32. American Mathematical Society (1967)

    Google Scholar 

  27. Hoare, C.: An axiomatic basis to computer programming. Communications of the ACM 12, 576–583 (1969)

    CrossRef  MATH  Google Scholar 

  28. Manna, Z.: The correctness of programs. Journal of Computer and System Sciences 3, 119–127 (1969)

    CrossRef  MathSciNet  Google Scholar 

  29. Matthews, J., Moore, J.S., Ray, S., Vroon, D.: Verification Condition Generation Via Theorem Proving. In: Hermann, M., Voronkov, A. (eds.) LPAR 2006. LNCS (LNAI), vol. 4246, pp. 362–376. Springer, Heidelberg (2006)

    CrossRef  Google Scholar 

  30. Horn, A., Tautschnig, M., Val, C., Liang, L., Mehlham, T., Grundy, J., Kroening, D.: Formal co-validation of low-level hardware/software interfaces. In: Jobstman, B., Ray, S. (eds.) Proceedings of the Formal Methods in Computer-Aided Design (FMCAD), pp. 121–128. ACM/IEEE (2013)

    Google Scholar 

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Davis, J., Slobodova, A., Swords, S. (2014). Microcode Verification – Another Piece of the Microprocessor Verification Puzzle. In: Klein, G., Gamboa, R. (eds) Interactive Theorem Proving. ITP 2014. Lecture Notes in Computer Science, vol 8558. Springer, Cham. https://doi.org/10.1007/978-3-319-08970-6_1

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  • DOI: https://doi.org/10.1007/978-3-319-08970-6_1

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-08969-0

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