Advertisement

Silicon and Germanium Junctionless Nanowire Transistors for Sensing and Digital Electronics Applications

  • Yordan M. GeorgievEmail author
  • Ran Yu
  • Nikolay Petkov
  • Olan Lotty
  • Adrian M. Nightingale
  • John C. deMello
  • Ray Duffy
  • Justin D. Holmes
Chapter
Part of the Engineering Materials book series (ENG.MAT.)

Abstract

In this chapter, we introduce two specific types of junctionless nanowire transistors (JNTs): (i) silicon-on-insulator (SOI) back-gated JNTs for sensing applications and (ii) germanium-on-insulator (GeOI) top-gated JNTs for digital logic applications. We discuss in detail the suitability of junctionless architecture for these particular applications and present results on device fabrication and characterisation. Back-gated JNTs of 45 different channel geometries (different numbers, lengths, and widths of channel nanowires) have been designed and fabricated with very high precision (down to 10 nm widths of the nanowires) on SOI wafers using a fully CMOS-compatible fabrication process. Electrical characterisation of the fabricated devices has demonstrated their excellent performance as back-gated JNTs. Furthermore, data from pH and streptavidin sensing experiments have proven their good sensing properties. These JNTs are among the smallest top-down fabricated nanowire sensing devices reported to date. Top-gated JNTs with Ge nanowire channels of widths down to 20 nm have been fabricated by a simple CMOS-compatible process on GeOI wafers with a highly p-doped (~1×1019 cm−3) top germanium layer. The fabricated devices have demonstrated decent output and transfer characteristics with relatively high I on /I off current ratios of up to 2.0 × 105 and steep subthreshold slopes of 189 mV/dec. To the best of our knowledge, these are the first reported Ge JNTs.

Keywords

Drain Current Electron Beam Lithography Subthreshold Slope Equivalent Oxide Thickness Inversion Mode 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

This work has been funded by the EU 7th Framework Programme under the SiNAPS project (no. 257856) and Science Foundation Ireland (SFI) under the grants no. 09/IN.1/I2602, 09/SIRG/I1623 and 10/IN.1/I2992.

References

  1. 1.
    International Technology Roadmap for Semiconductors (ITRS). http://www.itrs.net/ (2011)
  2. 2.
  3. 3.
    Ernst, T., et al.: Novel 3D integration process for highly scalable nano-beam stacked-channels GAA (NBG) Fin FETs with HfO2/TiN gate stack. In: IEEE International Electron Device Meeting (IEDM) Technical Digest, pp. 997–1001 (2006)Google Scholar
  4. 4.
    Buitrago, E., Fernandez-Bolaños, M., Georgiev, Y.M., Yu, R., Lotty, O., Holmes, J.D., Nightingale, A.M., Ionescu, A. M (2013) 3D silicon nanostructures for biosensing applications: functionalized 3D 7x20-array, vertically stacked SiNW FET for streptavidin sensing. In: 71st Annual Device Research Conference, DRC, Notre Dame, IN, USA (2013)Google Scholar
  5. 5.
    Colinge, J.P., et al.: SOI Gated Resistor: CMOS without Junctions. In: Proceedings of the IEEE International SOI Conference, paper 11.1 (2009)Google Scholar
  6. 6.
    Colinge, J.P., et al.: Nanowire transistors without junctions. Nat. Nanotechnol. 5–3, 225–229 (2010)CrossRefGoogle Scholar
  7. 7.
    Ferain, I., Colinge, C.A., Colinge, J.P.: Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature 479, 310–316 (2011)CrossRefGoogle Scholar
  8. 8.
    Colinge, J.P., et al.: Junctionless nanowire transistor (JNT): Properties and design guidelines. Solid-State Electron. 65–66, 33–37 (2011)CrossRefGoogle Scholar
  9. 9.
    Ansari, L., et al.: Simulation of junctionless Si nanowire transistors with 3 nm gate length. Appl. Phys. Lett. 97, 062105 (2010)CrossRefGoogle Scholar
  10. 10.
    Migita, S., et al.: Electrical performances of junctionless-FETs at the scaling limit (LCH = 3 nm). In: IEEE International Electron Device Meeting (IEDM) Technical Digest. pp. 191–194 (2012)Google Scholar
  11. 11.
    Park, C. –H., et al.: Comparative study of fabricated junctionless and inversion-mode nanowire FETs. In: Proceedings of the 69th Annual Device Research Conference, pp. 179–180. Santa Barbara, CA, USA (2011)Google Scholar
  12. 12.
    Gnani, E., et al.: Theory of the junctionless nanowire FET. IEEE Trans. Electron. Devices 58, 2903–2910 (2011)CrossRefGoogle Scholar
  13. 13.
    Su, C.-J., et al.: Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels. IEEE Electron Device Lett. 32, 521–523 (2011)CrossRefGoogle Scholar
  14. 14.
    Zhao, D.D., et al.: Junctionless Ge p-Channel metal–oxide–semiconductor field-effect transistors fabricated on ultrathin Ge-on-insulator substrate. Appl. Phys. Express 4, 031302 (2011)CrossRefGoogle Scholar
  15. 15.
    Cho, S., et al.: Silicon-compatible bulk-type compound junctionless field-effect transistor. In: Proceedings of ISDRS 2011, College Park, MD, USA, 7–9 Dec 2011Google Scholar
  16. 16.
    Yokoyama, M., et al.: Sub-10-nm extremely thin body InGaAs-on-Insulator MOSFETs on Si wafers with ultrathin Al2O3 buried oxide layers. Electron Device Lett. 32, 1218–1220 (2011)CrossRefGoogle Scholar
  17. 17.
    Jiang, J., et al.: Junctionless in-plane-gate transparent thin-film transistors. Appl. Phys. Lett. 99, 193502 (2011)CrossRefGoogle Scholar
  18. 18.
    Choi, S.-J., et al.: Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Device Lett. 32, 125–127 (2011)CrossRefGoogle Scholar
  19. 19.
    Aldegunde, M., et al.: Study of discrete doping—induced variability in junctionless nanowire MOSFETs using dissipative quantum transport simulations. IEEE Electron Device Lett. 33, 194–196 (2012)CrossRefGoogle Scholar
  20. 20.
    Taur, Y., et al.: On–off charge–voltage characteristics and dopant number fluctuation effects in junctionless double-gate MOSFETs. IEEE Trans. Electron Devices 59, 863–866 (2012)CrossRefGoogle Scholar
  21. 21.
    Dehdashti, A.N., et al.: Random dopant variation in junctionless nanowire transistors. In: Proceedings of the IEEE International SOI Conference, pp. 55–56 (2011)Google Scholar
  22. 22.
    Cui, Y., Lieber, C.M.: Functional nanoscale electronic devices assembled using silicon nanowire building blocks. Science 291(5505), 851–853 (2001)CrossRefGoogle Scholar
  23. 23.
    Cui, Y., Wei, Q., Park, H., Lieber, C.M.: Nanowire nanosensors for highly sensitive and selective detection of biological and chemical species. Science 293(5533), 1289–1292 (2001)CrossRefGoogle Scholar
  24. 24.
    Chen, K.I., Li, B.R., Chen, Y.T.: Silicon nanowire field-effect transistor-based biosensors for biomedical diagnosis and cellular recording investigation. Nano Today 6(2), 131–154 (2011)CrossRefGoogle Scholar
  25. 25.
    Elfström, N., Juhasz, R., Sychugov, I., Engfeldt, T., Karlström, A.E., Linnros, J.: Surface charge sensitivity of silicon nanowires: size dependence. Nano Lett. 7(9), 2608–2612 (2007)CrossRefGoogle Scholar
  26. 26.
    Stern, E., et al.: Label-free immunodetection with CMOS-compatible semiconducting nanowires. Nature 445(7127), 519–522 (2007)CrossRefGoogle Scholar
  27. 27.
    Heitzinger, C., Klimeck, G.: Computational aspects of the three-dimensional feature-scale simulation of silicon-nanowire field-effect sensors for DNA detection. J. Comput. Electron. 6(1), 387–390 (2007)CrossRefGoogle Scholar
  28. 28.
    Kim, A., et al.: Ultrasensitive, label-free, and real-time immunodetection using silicon field-effect transistors. Appl. Phys. Lett. 91(10), 103901–103903 (2007)CrossRefGoogle Scholar
  29. 29.
    Gao, P.A., Zheng, G., Lieber, C.M.: Subthreshold regime has the optimal sensitivity for nanowire FET biosensors. Nano Lett. 10, 547–552 (2009)CrossRefGoogle Scholar
  30. 30.
    Knopfmacher, O., Tarasov, A., Fu, W.Y., Wipf, M., Niesen, B., Calame, M., Schonenberger, C.: Nernst limit in dual-gated Si-nanowire FET sensors. Nano Lett. 10, 2268–2274 (2010)CrossRefGoogle Scholar
  31. 31.
    Buitrago, E., Fagas, G., Fernández-Bolanos, M.B., Georgiev, Y.M., Berthomé, M., Ionescu, A.M.: Junctionless silicon nanowire transistors for the tunable operation of a highly sensitive, low power sensor. Sens. Actuators, B 183, 1–10 (2013)CrossRefGoogle Scholar
  32. 32.
    Henschel, W., Georgiev, Y.M., Kurz, H.: Study of a high contrast process for hydrogen Silsesquioxane as a negative tone electron beam resist. J. Vac. Sci. Technol., B 21(5), 2018–2025 (2003)CrossRefGoogle Scholar
  33. 33.
    Georgiev, Y.M., Henschel, W., Fuchs, A., Kurz, H.: Surface roughness of hydrogen silsesquioxane as a negative tone electron beam resist. Vacuum 77(2), 117–123 (2005)CrossRefGoogle Scholar
  34. 34.
    Park, I., Li, Z., Li, X., Pisano, A.P., Williams, R.S.: Towards the silicon nanowire-based sensor for intracellular biochemical detection. Biosens. Bioelectron. 22, 2065–2070 (2007)CrossRefGoogle Scholar
  35. 35.
    Chen, Y., Wang, X., Erramilli, S., Mohanty, P., Kalinowski, A.: Silicon-based nanoelectronic field-effect pH sensor with local gate control. Appl. Phys. Lett. 89(22), 223512 (2006)CrossRefGoogle Scholar
  36. 36.
    Duffy, D.C., McDonald, J.C., Schueller, O.J.A., Whitesides, G.M.: Rapid prototyping of microfluidic systems in Poly(dimethylsiloxane). Anal. Chem. 70(23), 4974–4984 (1998)CrossRefGoogle Scholar
  37. 37.
    Satyanarayana, S., Karnik, R.N., Majumdar, A.: Stamp-and-stick room-temperature bonding technique for microdevices. J. Microelectromech. Syst. 14(2), 392–399 (2005)CrossRefGoogle Scholar
  38. 38.
    Pantisano, L., Trojman, L., Mitard, J., DeJaeger, B., Severi, S., Eneman, G., Crupi, G., Hoffmann, T., Ferain, I., Meuris, M., Heyns, M.: Fundamentals and extraction of velocity saturation in sub-100 nm (110)-Si and (100)-Ge. In: IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 52-53 (2008)Google Scholar
  39. 39.
    Natori, K.: Ballistic metal-oxide-semiconductor field effect transistor. J. Appl. Phys. 76, 4879 (1994)CrossRefGoogle Scholar
  40. 40.
    Kuhn, K.J., et al.: Past, present and future: SiGe and CMOS transistor scaling. ECS Trans. 33(6), 3–17 (2010)CrossRefGoogle Scholar
  41. 41.
    Colinge, J.-P., et al.: Reduced electric field in junctionless transistors. Appl. Phys. Lett. 96(7), 073510 (2010)CrossRefGoogle Scholar
  42. 42.
    Nakaharai, S., et al.: Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique. Appl. Phys. Lett. 83(17), 3516–3518 (2003)CrossRefGoogle Scholar
  43. 43.
    Deguet, C., et al.: Fabrication and characterisation of 200 mm germanium-on-insulator (GeOI) substrates made from bulk germanium. Electron. Lett. 42(7), 415–417 (2006)Google Scholar
  44. 44.
    Yu, R., et al.: Fabrication of germanium-on-insulator by low temperature direct wafer bonding. In: 10th IEEE International Conference on Solid-State and Integrated Circuit Technol (ICSICT): 953 (2010)Google Scholar
  45. 45.
    Namatsu, H., et al.: Three-dimensional siloxane resist for the formation of nanopatterns with minimum linewidth fluctuations. J. Vac. Sci. Technol., B 16, 69 (1998)CrossRefGoogle Scholar
  46. 46.
    Hobbs, R.G., Schmidt, M., Bolger, C.T., Georgiev Y.M., Xiu, F., Wang, K.L., Fleming, P., Morris, M.A., Djara, V., Yu, R., Colinge, J.-P., Petkov, N., Holmes, J.D.: Resist-substrate interface tailoring for generating high density arrays of Ge and Bi2Se3 nanowires by electron beam lithography. J. Vac. Sci. Technol. B 30(4), 041602(1)–041602(7) (2012)Google Scholar
  47. 47.
    Hobbs, R. G., Petkov, N., Holmes, J. D.: Methods and materials for lithography of a high resolution HSQ resist, European Patent Number: 11163598.3 (2012)Google Scholar
  48. 48.
    Yu, R., Das, S., Hobbs, R., Georgiev, Y., Ferain, I., Razavi, P., et al.: Top-down process of germanium nanowires using EBL exposure of hydrogen Silsesquioxane resist. In: IEEE 13th International Conference on Ultimate Integration on Silicon (ULIS). pp. 145–148 (2012)Google Scholar
  49. 49.
    Matsubara, H., Sasada, T., Takenaka, M., Takagi, S.: Evidence of low interface trap density in GeO2/Ge metal-oxide-semiconductor structures fabricated by thermal oxidation. Appl. Phys. Lett. 93, 032104 (2008)CrossRefGoogle Scholar
  50. 50.
    Xie, R., He, W., Yu, M., Zhu, C.: Effects of fluorine incorporation and forming gas annealing on high-k gated germanium metal-oxide-semiconductor with GeO2 surface passivation. Appl. Phys. Lett. 93, 073503–073504 (2008)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Yordan M. Georgiev
    • 1
    Email author
  • Ran Yu
    • 2
  • Nikolay Petkov
    • 1
  • Olan Lotty
    • 1
  • Adrian M. Nightingale
    • 3
  • John C. deMello
    • 3
  • Ray Duffy
    • 2
  • Justin D. Holmes
    • 1
  1. 1.Materials Chemistry and Analysis Group, Department of Chemistry and Tyndall National InstituteUniversity College CorkCorkIreland
  2. 2.Silicon Research GroupTyndall National InstituteCorkIreland
  3. 3.Nanostructured Materials and Devices Group, Department of ChemistryImperial College LondonLondonUK

Personalised recommendations