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Node Performance and Energy Analysis with the Sniper Multi-core Simulator

  • Trevor E. CarlsonEmail author
  • Wim Heirman
  • Kenzo Van Craeynest
  • Lieven Eeckhout
Conference paper

Abstract

Two major trends in high-performance computing, namely, larger numbers of cores and the growing size of on-chip cache memory, are creating significant challenges for evaluating the design space of future processor architectures. Fast and scalable simulations are therefore needed to allow for sufficient exploration of large multi-core systems within a limited simulation time budget. By bringing together accurate high-abstraction analytical models with fast parallel simulation, architects can trade off accuracy with simulation speed to allow for longer application runs, covering a larger portion of the hardware design space. Sniper provides this balance allowing long-running simulations to be modeled much faster than with detailed cycle-accurate simulation, while still providing the detail necessary to observe core-uncore interactions across the entire system. With per-function advanced visualization and coupled power and energy simulations, the Sniper multi-core simulator can provide a fast and accurate way both to understand and optimize software for current and future hardware systems.

Keywords

Cache Coherence Simulation Speed Interval Simulation Barrier Synchronization Branch Predictor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgements

We thank Mathijs Rogiers for his invaluable work on the visualization features of Sniper and the anonymous reviewers for their valuable feedback. This work is supported by Intel and the Institute for the Promotion of Innovation through Science and Technology in Flanders (IWT). Additional support is provided by the European Research Council under the European Community’s Seventh Framework Programme (FP7/2007–2013) / ERC Grant agreement no. 259295. Experiments were run on computing infrastructure at the ExaScience Lab, Leuven, Belgium; the Intel HPC Lab, Swindon, UK; and the VSC Flemish Supercomputer Center.

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Trevor E. Carlson
    • 1
    Email author
  • Wim Heirman
    • 2
  • Kenzo Van Craeynest
    • 1
  • Lieven Eeckhout
    • 1
  1. 1.Ghent UniversityGentBelgium
  2. 2.Intel, ExaScience LabLeuvenBelgium

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