Mixed-Signal IP Design Challenges in 20 nm, FinFET and Beyond

Abstract

Deep sub-micron (including 20 nm and FinFET) processes have led to significant design challenges. These include process spread, I/O voltage limitations, transistor reliability, limitations in transistor W and L, restrictive physical design rules, device matching, simulation verification including parasitics, and electromigration. This chapter discusses these challenges and ways to address them, including using cascoded transistors to prevent over-voltage stress on devices, running LPE simulation verification which includes metal resistances, and using compound transistors which have DC characteristics similar to long-channel transistors.