Abstract
This chapter discusses how digital assistance can be leveraged in the design of analog to digital converters. Different types of digital assistance are defined, and a few of the possible applications selected for detailed discussion. Finally, an example of an ADC implementation heavily leveraging digital assistance is presented.
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References
Z. G. Boyacigiller, B. Weir, P. D. Bradshaw, “An Error-Correcting 14b/20μs CMOS A/D Converter,” IEEE ISSCC 1981
B. Murmann, “Digitally assisted data converter design,” IEEE ESSCIRC, September 2013, pp. 24–31
B. Murmann, “ADC Performance Survey 1997-2013,” [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html
B. Setterberg, et al., “A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction,” IEEE ISSCC 2013
G. Van der Plas, et al., “A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90 nm Digital CMOS Process,” IEEE ISSCC 2006
B. Verbruggen, et al., “A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40 nm digital CMOS,” IEEE JSSC, Vol. 47, No. 12, December 2012, pp. 2880–2887
A. Shikata, et al., “A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS,” IEEE JSSC, Vol. 47, No. 4, April 2012, pp. 1022–1030
T. Kobayashi, et al., “A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture,” IEEE JSSC, Vol. 28, No. 4, April 1993, pp. 523–527
M. Miyahara, et al., “A low-offset latched comparator using zero-static power dynamic offset cancellation technique,” IEEE ASSCC 2009
M.-J. E. Lee, et al., “Low-power area-efficient high-speed I/O circuit techniques,” IEEE JSSC, Vol. 35, No. 11, November 2000, pp. 1591–1599
F. H. Gebara, et al., “A body-driven offset cancellation technique in PD-SOI,” International Conference on Microelectronics, May 2004, Vol. 2, pp. 567–570
B. Verbruggen, et al., “A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS,” IEEE JSSC, Vol. 44, No. 3, March 2009, pp. 874–882
Y.-S. Shu, “A 6b 3GS/s 11mW Fully Dynamic Flash ADC in 40 nm CMOS with Reduced Number of Comparators,” Symposium on VLSI Circuits, June 2012, pp. 26–27
V. H.-C. Chen, et al., “An 8.5mW 5GS/s 6b flash ADC with dynamic offset calibration in 32 nm CMOS SOI,” Symposium on VLSI Circuits, June 2013, pp. 264–265
V. Giannini, et al., “An 820 μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90 nm Digital CMOS,” IEEE ISSCC 2008
G. Van der Plas, et al., “A 150 MS/s 133 μW 7 bit ADC in 90 nm Digital CMOS,” IEEE JSSC, Vol. 43, No. 12, December 2008, pp. 2631–2640
Y. Nakajima, et al., “A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture,” IEEE JSSC, Vol. 45, No. 4, April 2010, pp. 707–718
Z. Gu, et al., “A novel self-calibrating scheme for video-rate 2-step flash analog-to-digital converter,” IEEE International Symposium on Circuits and Systems, May 1992, Vol. 2, pp. 601–604
B. Verbruggen, et al., “A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28 nm digital CMOS,” Symposium on VLSI Circuits, June 2013, pp. 268–269
J. K Fiorenza, et al., “Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies,” IEEE JSSC, Vol. 41, No. 12, December 2006, pp. 2658–2668
B. Hershberg, et al., “Ring Amplifiers for Switched Capacitor Circuits,” IEEE JSSC, Vol. 47, No. 12, December 2012, pp. 2928–2942
B. Murmann, et al., “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE JSSC, Vol. 38, No. 12, December 2003, pp. 2040–2050
M. Anthony, et al., “A process-scalable low-power charge-domain 13-bit pipeline ADC,” Symposium on VLSI Circuits, June 2008, pp. 222–223
N. Dolev, et al., “A 12-bit, 200-MS/s, 11.5-mW pipeline ADC using a pulsed bucket brigade front-end,” Symposium on VLSI Circuits, June 2013, pp. 98–99
J. Hu, et al., “A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification,” IEEE JSSC, Vol. 44, No. 4, April 2009, pp. 1057–1066
S.-H. W. Chiang, et al., “A 10-Bit 800-MHz 19-mW CMOS ADC,” Symposium on VLSI Circuits, June 2013, pp. 100–101
L. Brooks, et al., “Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation,” IEEE TCAS I, Vol. 55, No. 10, November 2008, pp. 2969–2979
M. J. M. Pelgrom, et al., “Matching properties of MOS transistors,” IEEE JSSC, Vol. 24, No. 5, October 1989, pp. 1433–1439
P. Harpe, et al., “A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction,” IEEE ISSCC 2013
N. Verma, et al., “A 25/spl mu/W 100kS/s 12b ADC for wireless micro-sensor applications,” IEEE ISSCC 2006
C.-C. Liu, et al., “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE JSSC, Vol. 45, No. 4, April 2010, pp. 731–740
E. J. Siragusa, et al., “Gain error correction technique for pipelined analogue-to-digital converters,” Electronics Letters, vol. 36, no. 7, March 2000, pp. 617–618
Acknowledgments
The author would like to thank Masao Iriguchi, Manuel de la Guia Solaz, Guy Glorieux, Kazuaki Deguchi, Badr Malki, Ewout Martens and Jan Craninckx for their contributions to this paper.
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Verbruggen, B. (2015). Digitally Assisted Analog to Digital Converters. In: Harpe, P., Baschirotto, A., Makinwa, K. (eds) High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-07938-7_2
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DOI: https://doi.org/10.1007/978-3-319-07938-7_2
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