Formalization of fUML: An Application to Process Verification

  • Yoann Laurent
  • Reda Bendraou
  • Souheib Baarir
  • Marie-Pierre Gervais
Conference paper

DOI: 10.1007/978-3-319-07881-6_24

Part of the Lecture Notes in Computer Science book series (LNCS, volume 8484)
Cite this paper as:
Laurent Y., Bendraou R., Baarir S., Gervais MP. (2014) Formalization of fUML: An Application to Process Verification. In: Jarke M. et al. (eds) Advanced Information Systems Engineering. CAiSE 2014. Lecture Notes in Computer Science, vol 8484. Springer, Cham

Abstract

Much research work has been done on formalizing UML Activity Diagrams for process modeling to verify different kinds of soundness properties (deadlock, unreachable activities and so on) on process models. However, these works focus mainly on the control-flow aspects of the process and have done some assumptions on the precise execution semantics defined in natural language in the UML specification. In this paper, we define a first-order logic formalization of fUML (Foundational Subset of Executable UML), the official and precise operational semantics of UML, in order to apply model checking techniques and therefore verify the correctness of fUML-based process models. Our formalization covers the control-flow, data-flow, resources, and timing dimensions of processes in a unified way. A working implementation based on the Alloy language has been developed. The implementation showed us that many kinds of behavioral properties not commonly supported by other approaches and implying multiple dimensions of the process can be efficiently checked.

Keywords

Formalization Model-checking fUML Alloy 

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Yoann Laurent
    • 1
  • Reda Bendraou
    • 1
  • Souheib Baarir
    • 1
    • 2
  • Marie-Pierre Gervais
    • 1
    • 2
  1. 1.Sorbonne Universites, UPMC Univ Paris 06, UMR 7606, LIP6ParisFrance
  2. 2.Universite Paris Ouest Nanterre La DéfenseNanterreFrance

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