Implementation of Audio Data Packet Encryption Synchronization Circuit

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 298)

Abstract

The paper chooses the cyclone the second generation of the FPGA chip as the gate array (FPGA) used by AES encryption algorithm. The paper also uses speech codec WM8731 chip to realize eight voice and data coding. Then the paper refers to the PCM frame structure TS0 times lot function design code word synchronization. At last, the paper also uses AES128 grouping encryption algorithm to encrypt digital signal, and voice encryption is realized on the FPGA hardware.

Keywords

encryption algorithm FPGA chip speech coding encryption synchronization 

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  1. 1.Electronic EngineeringHeilongjiang UniversityHarbinChina

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