Parallel ASIP Based Design of Turbo Decoder

  • F. F. Zakaria
  • P. Ehkan
  • M. N. M. Warip
  • M. Elshaikh
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 315)

Abstract

Application Specific Instruction-set Processor (ASIP) has a general-purpose architecture that can be modified and used in a variety of applications. However, this increases the power and memory utilization and affects the functionality and efficiency of ASIP. This paper is defining the flexibility of ASIP for Turbo decoding in term of its functionality and architecture for specific applications such as DVB-RCS, 3GPP. The proposed architecture has a dedicated SIMD (Single Instruction Set Multiple Data), coupled with distributed memory based ASIP. It has been concluded in this paper that ASIP facilitates parallelism at different levels, thereby, increasing the efficiency, power consumption, and processing time.

Keywords

Application-specific instruction-set processor Bahl-Cocke-Jelinek-Raviv (BCJR) Turbo decoding recognition 

References

  1. 1.
    Berrou, C., Glavieux, A., Thitimasjhima, P.: Near Shannon limit error-correcting coding and decoding: turbo codes, ICC Geneva, (1993)Google Scholar
  2. 2.
    Prescher, G., Gemmeke, T., Noll, T.: A parameterizable low-power high-throughput turbo decoder. In proceedings Of ICASSP vol. 05, pp. 25–28 Pennsylvania (2005)Google Scholar
  3. 3.
    Gnaëdig, D., Boutillon, E., Jezequel, M., Gaudet, V., Gulak, G.: “On multiple slice turbo code” The 3rd International Symposium on Turbo Codes and Related Topics, pp.343–346 Brest, France (2003)Google Scholar
  4. 4.
    Keutzer, K., Malik, S., Newton, A.R.: “From ASIC to ASIP- next design discontinuity”. In: IEEE International Conference on Computer Design: VLSI in computers and processors, pp. 84–90, IEEE Computer Society, Washington (2002)Google Scholar
  5. 5.
    Vogt,T., Wehn, N.: “A reconfigurable application specific instruction set processor for viterbi and Log-MAP decoding”. In: IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS ‘06 pp. 142–147, Banff, Canada (2006)Google Scholar
  6. 6.
    Muller, O., Baghdadi, A., Jezequel, M.:“ASIP-based multiprocessor SoC design for simple and double binary turbo decoding”. In: Proceedings Design, Automation And Test In Europe, pp. 1330–1335, Munich (2006)Google Scholar
  7. 7.
    Muller, O., Baghdadi, A., Jezequel, M.:“From application to ASIP-based FPGA prototype: a case study on turbo decoding”. In: IEEE/IFIP International Symposium on Rapid System Prototyping, Monterey, (2008)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  • F. F. Zakaria
    • 1
  • P. Ehkan
    • 1
  • M. N. M. Warip
    • 1
  • M. Elshaikh
    • 1
  1. 1.School of Computer and Communication EngineeringUniversiti Malaysia PerlisArauMalaysia

Personalised recommendations