TSV Macro-Modeling Framework

Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

Macro-modeling of through silicon via (TSV) interconnects plays an important role in signal integrity (SI), power integrity (PI), and timing analysis of large 3D digital systems by reducing the CPU memory consumption and simulation time requirement. Hence, modeling methodologies are required to perform these simulations efficiently. This chapter presents a complete set of self-consistent equations including self and coupling terms for capacitance of general multi-TSV structures. The error when using the closed-form expressions as compared to a field solver is < 7 %. As TSV parasitic capacitance is less than other conventional input/output (I/O) structures’ capacitance; therefore, TSV technology results in lower I/O power consumption, which makes it suitable for low-power applications.

Keywords

Macro-modeling Framework Coupling Circuit solver Multi-stacked Arrangements Neighboring Signal Ground Error Matrix ABCD parameters S-parameter Cascaded Chaining 

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Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.Mentor GraphicsHeliopolisEgypt
  2. 2.The American University (New Cairo) and Zewail City of Science and Technology (6th of October City)New CairoEgypt

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