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TSV Verification

Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

This chapter discusses the validation of the developed through silicon via (TSV) lumped element model and the closed form expressions of its elements’ values versus the electromagnetic (EM) simulations in the frequency domain as well as the accuracy of the TSV model in the time domain and the analysis of the impact of a TSV on circuit performance. Moreover, the validation against device simulation is performed. The parameters’ values of the TSV model are fitted to the simulated scattering (S) parameters up to 100 GHz with an error < 5 %.

Keywords

Verification Validation Frequency domain Time domain Port Circuit performance Eye diagram Device simulation Fabrication Stacking Wafer Bonding Formation Alignment Thining Etching Filling 

References

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    Mentor Graphics, Eldo classic: foundry certified SPICE accurate circuit simulation (n.d.), http://www.mentor.com/products/ic_nanometer_design/analog-mixed-signal-verification/eldo
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Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.Mentor GraphicsHeliopolisEgypt
  2. 2.The American University (New Cairo) and Zewail City of Science and Technology (6th of October City)New CairoEgypt

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