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Implementation of Compressed Brute-Force Pattern Search Algorithm Using VHDL

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Advanced Computing, Networking and Informatics- Volume 2

Part of the book series: Smart Innovation, Systems and Technologies ((SIST,volume 28))

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Abstract

High speed and always-on network access is becoming commonplace around the world, creating a demand for increased network security. Network Intrusion Detection Systems (NIDS) attempt to detect and prevent attacks from the network using pattern-matching rules. Data compression methods are used to reduce the data storage requirement. Searching a compressed pattern in the compressed text reduces the internal storage requirement and computation resources. In this paper we implemented search process to perform compressed pattern matching in binary Huffman encoded texts. Brute-Force Search algorithm is applied comparing a single bit per clock cycle and comparing an encoded character per clock cycle. Pattern matching processes are evaluated in terms of clock cycle.

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References

  1. Amir, A., Benson, G.: Two Dimensional Compressed Matching. In: Proceedings of Data Compression Conference (DCC), pp. 279–288 (1992)

    Google Scholar 

  2. Huffman, D.A.: A method for the construction of minimum-redundancy codes. In: Proceedings of the IRE, pp. 1098–1101 (1952)

    Google Scholar 

  3. http://www.aldec.com/downloads

  4. Dubrawsky, I.: Firewall Evolution - Deep Packet Inspection (2003)

    Google Scholar 

  5. Mukherjee, B., Heberlein, L.T., Levitt, K.N.: Network Intrusion Detection. IEEE Network, 26–48 (1994)

    Google Scholar 

  6. Fisk, M., Varghese, G.: An analysis of fast string matching applied to content based for-warding and intrusion detection. In: Technical Report CS2001-0670, University of California (2002)

    Google Scholar 

  7. Buboltz, J., Kocak, T.: Front End Device for Content Networking. In: Proceedings of the Conference on Design, Automation and Test in Europe (2008)

    Google Scholar 

  8. Karp, R.M., Rabin, M.O.: Efficient randomized pattern-matching algorithms. IBM Journal of Research and Development 31(2), 249–260 (1987)

    Article  MathSciNet  MATH  Google Scholar 

  9. Knuth, D.E., Morris, J., Pratt, V.R.: Fast pattern matching in strings. SIAM Journal on Computing (1977)

    Google Scholar 

  10. Baker, Z.K., Prasanna, Z.K.,, V.K.: A methodology for synthesis of efficient intrusion detection systems on FPGAs. In: IEEE Symposium on Field-Programmable Custom Computing Machines (2004)

    Google Scholar 

  11. Sidhu, R., Mei, A., Prasanna, V.K.: String matching on multi-content FPGAs using self-reconfiguration. In: Proceedings of FPGA 1999 (1999)

    Google Scholar 

  12. Ashenden, P.J.: Modeling digital systems using VHDL. In: Proceedings of Potentials of IEE, vol. 17(2), pp. 27–30 (1998)

    Google Scholar 

  13. Sidhu, R., Prasanna, V.K.: Fast regular expression matching using FPGAs. In: IEEE Symposium on Field-Programmable Custom Computing Machines (2001)

    Google Scholar 

  14. Mukherjee, A., Acharya, T.: VlSI Algorithms for Compressed Pattern Search Using Tree Based Codes. In: Proceedings of the IEEE International Conference on Application Specific Array Processors (1995)

    Google Scholar 

  15. Clark, C.R., Schimmel, D.E.: Efficient reconfigurable logic circuit for matching complex network intrusion detection patterns. In: Cheung, P.Y.K., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 956–959. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

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Correspondence to Lokesh Sharma .

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© 2014 Springer International Publishing Switzerland

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Sharma, L., Sharma, B., Sharma, D.P. (2014). Implementation of Compressed Brute-Force Pattern Search Algorithm Using VHDL. In: Kumar Kundu, M., Mohapatra, D., Konar, A., Chakraborty, A. (eds) Advanced Computing, Networking and Informatics- Volume 2. Smart Innovation, Systems and Technologies, vol 28. Springer, Cham. https://doi.org/10.1007/978-3-319-07350-7_66

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  • DOI: https://doi.org/10.1007/978-3-319-07350-7_66

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-07349-1

  • Online ISBN: 978-3-319-07350-7

  • eBook Packages: EngineeringEngineering (R0)

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