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SAT Based Scheduling in High Level Synthesis

  • Sudeshna Kundu
  • Khushbu Chandrakar
  • Suchismita Roy
Conference paper
Part of the Smart Innovation, Systems and Technologies book series (SIST, volume 28)

Abstract

High level synthesis is the process of generating the register transfer level (RTL) design from the behavioural description. Time-constrained scheduling minimizes the requirement of functional units under a given time constraint and Resource-constrained scheduling minimizes the number of control steps under given resource constraint. A PB-SAT based approach which concentrates on operation scheduling, and also optimizes the number of resources and control steps is proposed here. Time-constrained and Resource-constrained based scheduling is formulated as a Pseudo-boolean satisfiability (PB-SAT) based problem and a SAT solver is used for finding the optimum schedule and minimum number of functional unit and control steps satisfying all constraints.

Keywords

High-level synthesis Time-constrained scheduling Resource-constrained scheduling PB-SAT 

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Sudeshna Kundu
    • 1
  • Khushbu Chandrakar
    • 1
  • Suchismita Roy
    • 1
  1. 1.Department of Computer Science and EngineeringNational Institute of TechnologyDurgapurIndia

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