Architecting Fabricated Implant in Interconnect for Multi-core Processor

  • Ram Prasad Mohanty
  • Ashok Kumar Turuk
  • Bibhudatta Sahoo
Conference paper
Part of the Smart Innovation, Systems and Technologies book series (SIST, volume 28)


In this paper, we analyze the effect of interconnect on multi-core processors and have proposed a novel highly scalable on-chip interconnection mechanism for multi-core processors. As the number of cores increases, traditional on-chip interconnect like bus and crossbar proves to be low in efficiency as well as suffer from poor scalability. In order to get rid of the scalability and efficiency issues in these traditional interconnects, ring based design has been proposed. But with the steady growth in number of cores have rendered the ring interconnect too infeasible. Thus, novel interconnect designs are proposed for the future multi-core processors for enhancement in the scalability. In this paper, we analyze and compare the interconnect of two existing multi-core processors named Multi-core Processor with Internal Network(MPIN) and Mult-core processor with Ring Network(MPRN). We have also proposed a highly scalable and efficient interconnect named as fabricated Implant in Interconnect for multi-core processors. The placement of cores and cache in a network is proved to be highly crucial for system performance. The benchmark results are presented by using a full system simulator. Results show that, by using the proposed on-chip interconnect, compared with the MPIN and MPRN, the execution time are significantly reduced for three applications.


Multi-core Processor Performance analysis Interconnect Cache Dependency 


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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Ram Prasad Mohanty
    • 1
  • Ashok Kumar Turuk
    • 1
  • Bibhudatta Sahoo
    • 1
  1. 1.Department of Computer Science and EngineeringNational Institute of TechnologyRourkelaIndia

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