Sampled Data Systems

  • Konstantinos G. PapadopoulosEmail author


In this chapter, analytical tuning rules for digital PID type-I, type-II, type-III control loops are presented. Controller parameters are determined explicitly as a function of the process parameters and the sampling time \(T_\mathrm{s}\) of the controller. For developing the proposed theory in type-I, type-II control loops, a generalized single-input single-output stable process model is used consisting of \(n\)-poles, \(m\)-zeros plus unknown time delay-\(d\). As far as type-III control loops is concerned the principle of pole-zero cancellation according to the method proposed in Sect.  5.2.1, see [3], is followed. The derivation of the proposed PID control law lies in the principle of the Magnitude Optimum criterion and the optimization conditions proved in Appendix A.1 are used for extracting the explicit solution. For all control loop types, a performance comparison is presented in terms of simulation examples. The comparison focuses on the effect of the sampling time \(T_\mathrm{s}\) to the control loops response both in the time and frequency domain.


Pole-zero Cancellation Digital Control Loop Output Disturbance Rejection Analog Control Action Nonminimum Phase Process 
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  1. 1.
    Papadopoulos KG, Margaris NI (2012) Extending the symmetrical optimum criterion to the design of PID type-p control loops. J Process Control 12(1):11–25CrossRefGoogle Scholar
  2. 2.
    Papadopoulos KG, Papastefanaki EN, Margaris NI (2013) Explicit analytical PID tuning rules for the design of type-III control loops. IEEE Trans Ind Electron 60(10):4650–4664CrossRefGoogle Scholar
  3. 3.
    Papadopoulos KG, Tselepis ND, Margaris NI (2013) Type III control loops-digital PID controller design. J Process Control 23(10):1401–1414CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.ATDDABB IndustriesTurgiSwitzerland

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