Abstract
The previous chapter proposed a generic framework for modeling reconfiguration. As illustrated in Fig. 4.1 (same as Fig. 1.5), the simulation-only layer is a collection of behavioral models that emulate the physical layer and capture the inter-layer interactions of DPR. The simulation-only layer is capable of exposing fabric-independent functional bugs in DRS designs.
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Notes
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Similar to Fig. 3.5, the application logic is lightly shaded, reconfiguration machinery is moderately shaded, and simulation-only artifacts are indicated by open boxes.
References
J. Aynsley, OSCI TLM-2.0 Language Reference Manual, Open SystemC Initiative (OSCI) (2009) [online]. Available: http://www.systemc.org/home
M. Glasser, Open Verification Methodology Cookbook (Mentor Graphics Corporation, 2009) [online]. Available: http://www.mentor.com/cookbook
IEEE Standard 1800-2005: SystemVerilog – Unified Hardware Design, Specification, and Verification Language (The Institute of Electrical and Electronics Engineers, Inc., New York, 2005)
IEEE Standard 1666-2011: SystemC Language Reference Manual (The Institute of Electrical and Electronics Engineers, Inc., 2012)
Y.S. Iskander, C.D. Patterson, S.D. Craven, High-level abstractions and modular debugging for FPGA design validation. ACM Trans. Reconfigurable Technol. Syst. (TRETS) 7(2), 2:1–2:24 (2014)
W. Luk, N. Shirazi, P.Y. Cheung, Compilation tools for run-time reconfigurable designs, in IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, 1997, pp. 56–65
Mentor Graphics Corporation, ModelSim SE User’s Manual (Software Version 6.5g) (Mentor Graphics Corporation, Wilsonville, 2010). http://www.mentor.com/products/fv/modelsim/
M. Montoreano, Transaction Level Modeling Using OSCI TLM 2.0 (Open SystemC Initiative (OSCI), 2007). http://www.accellera.org/downloads/standards/systemc/accept_license/accepted_download/TLM2_Whitepaper.pdf
K. Paulsson, U. Viereck, M. Hubner, J. Becker, Exploitation of the external JTAG interface for internally controlled configuration Readback and self-reconfiguration of Spartan 3 FPGAs, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Montpellier 2008, pp. 304–309
A. Raabe, P.A. Hartmann, J.K. Anlauf, ReChannel: describing and simulating reconfigurable hardware in SystemC. ACM Trans. Des. Autom. Electron. Syst. 13(1), 15:1–15:18 (2008)
I. Robertson, J. Irvine, A design flow for partially reconfigurable hardware. ACM Trans. Embed. Comput. Syst. (TECS) 3(2), 257–283 (2004)
Xilinx Inc., ChipScope Pro 12.1 Software and Cores (UG029) (Xilinx Inc., San Jose, 2010). http://www.xilinx.com/support.html
Xilinx Inc., Partial Reconfiguration User Guide (UG702) (Xilinx Inc., San Jose, 2010). http://www.xilinx.com/support.html
Xilinx Inc., Synthesis and Simulation Design Guide (Xilinx Inc., San Jose, 2010). http://www.xilinx.com/support.html
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Gong, L., Diessel, O. (2015). Getting Started with Verification. In: Functional Verification of Dynamically Reconfigurable FPGA-based Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-06838-1_4
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DOI: https://doi.org/10.1007/978-3-319-06838-1_4
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