Abstract
Fault tolerance techniques aiming to detect transient effects can be mainly divided in three broad categories: (1) software-based techniques , (2) hardware-based techniques and (3) hybrid techniques . Fault tolerance techniques can be applied at different levels of implementation, starting from the software level down to the architecture description level, the logical and transistor level, until the layout level. In this book, we will focus on hybrid techniques applied at software level.
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© 2014 Springer International Publishing Switzerland
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Azambuja, J., Kastensmidt, F., Becker, J. (2014). Fault Tolerance Techniques for Processors. In: Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors. Springer, Cham. https://doi.org/10.1007/978-3-319-06340-9_3
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DOI: https://doi.org/10.1007/978-3-319-06340-9_3
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Publisher Name: Springer, Cham
Print ISBN: 978-3-319-06339-3
Online ISBN: 978-3-319-06340-9
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