Case Studies

Chapter
Part of the Embedded Systems book series (EMSY)

Abstract

In this chapter we first evaluate the CSAR debug approach and infrastructure in Sect. 8.1. We subsequently use an illustrative GALS SOC model to evaluate specifically the communication-centric and abstraction-based aspects of the CSAR debug approach in more detail. We describe the application that runs on this SOC, its hardware architecture, and its internal clock domains in Sect. 8.2. We apply our DfD flow to the RTL implementation of this SOC in Sect. 8.3 and report on its effectiveness and efficiency. We also describe how we customize our CSARDE for use with this particular SOC. Even though this SOC is intentionally kept small for illustration purposes, we show in Sect. 8.4 that the factors identified in Chaps.  2 and  3 already complicate the debugging of an SOC this size. We also discuss in Sect. 8.4 how the CSAR debug approach and infrastructure reduces or eliminates the impact of each factor. In Sect. 8.5, we introduce examples of three different error types in the implementation of this SOC. These error types are (1) a permanent, certain error , (2) a transient, certain error , and (3) a transient, uncertain error . We subsequently describe how we can use the CSAR debug approach and infrastructure to localize these three example errors. We conclude this chapter with a summary in Sect. 8.6.

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  1. 1.NXP SemiconductorsEindhovenThe Netherlands
  2. 2.Faculty of Electrical EngineeringEindhoven University of TechnologyEindhovenThe Netherlands

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