CSAR Debug Overview

  • Bart Vermeulen
  • Kees Goossens
Part of the Embedded Systems book series (EMSY)


In this chapter we introduce our communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug approach and its associated infrastructure. This approach and its infrastructure meets the post-silicon debug requirements, identified in Chap.  1, and reduces the effects of the complicating factors for debugging, identified in Chaps.  2 and  3. We first give an introduction of the CSAR debug approach and its on-chip and off-chip debug infrastructure in Sect. 4.1, and show how it is used. In Sect. 4.2, we detail our rationale behind the CSAR debug approach, by describing in detail how this approach addresses the debug requirements and complicating factors for debugging. The CSAR debug approach imposes requirements on the on-chip and off-chip debug infrastructure. We review and formulate these requirements in Sect. 4.3. We conclude this chapter with a summary in Sect. 4.4.


  1. 1.
    IEEE. IEEE Standard Test Access Port and Boundary-Scan Architecture - IEEE Std 1149.1-2001. IEEE Press, 2013.Google Scholar
  2. 2.
    R. Milner. Communication and concurrency. Prentice-Hall, 1989.Google Scholar
  3. 3.
    Bart Vermeulen and Kees Goossens. Debugging Multi-Core Systems on Chip. In George Kornaros, editor, Multi-Core Embedded Systems, chapter 5, pages 153–198. CRC Press/Taylor & Francis Group, 2010.Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  1. 1.NXP SemiconductorsEindhovenThe Netherlands
  2. 2.Faculty of Electrical EngineeringEindhoven University of TechnologyEindhovenThe Netherlands

Personalised recommendations