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Introduction

Chapter
Part of the Embedded Systems book series (EMSY)

Abstract

We start this chapter in Sect. 1.2 by reviewing the trends, challenges, and methodologies used in the implementation, verification, and validation of SOCs. We describe a generic and commonly-used post-silicon debug process in Sect. 1.3, which helps debug engineers with the localization of the root cause of problems that occur post-silicon. In Sect. 1.4, we show however that this generic process has requirements that cannot easily be met post-silicon. We outline our proposed solution and the organization of this book in Sect. 1.5. In Sect. 1.6 we provide an overview of the contributions of this book with respect to the state of the art in post-silicon debug. We conclude this chapter with a summary in Sect. 1.7.

References

  1. 1.
    Miron Abramovici, Paul Bradley, Kumar Dwarakanath, Peter Levin, Gerard Memmi, and Dave Miller. A reconfigurable design-for-debug infrastructure for SoCs. In Proc. Design Automation Conference, pages 7–12, New York, NY, USA, 2006. Association for Computing Machinery, Inc.Google Scholar
  2. 2.
    ARM. AMBA specification. rev. 2. 0, 1999.Google Scholar
  3. 3.
    ARM Limited. AMBA AXI Protocol Specification, June 2003.Google Scholar
  4. 4.
    Daniel P. Bovet and Marco Cesati. Understanding the linux kernel. O’Reilly, November 2005.Google Scholar
  5. 5.
    Jack Browne. 318 engineers surveyed on top core frequencies and noc use issues, November 2012.Google Scholar
  6. 6.
    Theo A. C. M. Claasen. System on a chip: Changing ic design today and in the future. IEEE Micro, 23(3):20–26, May 2003.Google Scholar
  7. 7.
    A. Danial. Cloc - count lines of code, 2012.Google Scholar
  8. 8.
    Giovanni De Micheli and Luca Benini, editors. Networks on Chips: Technology and Tools. The Morgan Kaufmann Series in Systems on Silicon. Morgan Kaufmann Publishers Inc., July 2006.Google Scholar
  9. 9.
    Harry Foster. Wilson research group and mentor graphics, 2012 functional verification study. blog, 2013.Google Scholar
  10. 10.
    Jeroen Geuzebroek and Bart Vermeulen. Integration of Hardware Assertions in Systems-on-Chip. In Proc. IEEE International Test Conference, 2008.Google Scholar
  11. 11.
    Sandeep Kumar Goel and Bart Vermeulen. Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. Journal of Electronic Testing: Theory and Applications, 19(4):407–416, 2003.CrossRefGoogle Scholar
  12. 12.
    Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, and Steven Oostdijk. Test infrastructure design for the nexperia home platform pnx8550 system chip. In Proc. Design, Automation, and Test in Europe conference, 2004.Google Scholar
  13. 13.
    K. Goossens, B. Vermeulen, R. van Steeden, and M. Bennebroek.. In Proc. International Symposium on Networks on Chip, pages 95–106, 5 2007.Google Scholar
  14. 14.
    Kees Goossens, Bart Vermeulen, and Ashkan Beyranvand Nejad. A High-Level Debug Environment for Communication-Centric Debug. In Proc. Design, Automation, and Test in Europe conference, 2009.Google Scholar
  15. 15.
    Hadas Haran. What’s stopping you from improving your time to market?, April 2011.Google Scholar
  16. 16.
    IBM. Revenue lost by being late to market, 2006.Google Scholar
  17. 17.
    International Roadmap Committee. The international technology roadmap for semiconductors (itrs), 2012.Google Scholar
  18. 18.
    Axel Jantsch and Hannu Tenhunen, editors. Networks on Chip. Kluwer Academic Publishers, 2003.Google Scholar
  19. 19.
    A.C.J. Kienhuis. Design Space Exploration of Stream-based Dataflow Architectures: Methods and Tools. PhD thesis, Delft University of Technology, 1999.Google Scholar
  20. 20.
    Jerry Kuo. IP-STB introduction. NXP Semiconductors, 2007.Google Scholar
  21. 21.
    G. E. Moore. Cramming More Components onto Integrated Circuits. Electronics, 38(8):114–117, April 1965.Google Scholar
  22. 22.
    Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, and Shakti Kapoor. Bridging pre-silicon verification and post-silicon validation. In Proc. Design Automation Conference, 2010.Google Scholar
  23. 23.
    Sudeep Pasricha and Nikil Dutt. On-Chip Communication Architectures. Systems on Silicon. Morgan Kaufmann Publishers Inc., 2008.Google Scholar
  24. 24.
    G.J. Van Rootselaar and B. Vermeulen. Silicon debug: scan chains alone are not enough. In Proc. IEEE International Test Conference, pages 892–902, 1999.Google Scholar
  25. 25.
    B. Vermeulen and G.J. van Rootselaar. Silicon debug of a co-processor array for video applications. In Proc. High-Level Design Validation and Test Workshop, pages 47–52, 2000.Google Scholar
  26. 26.
    B. Vermeulen and S.K. Goel. Design for debug: catching design errors in digital chips. Design Test of Computers, IEEE, 19(3):35–43, 5 2002.Google Scholar
  27. 27.
    Bart Vermeulen and Kees Goossens. A Network-on-Chip Monitoring Infrastructure for Communication-centric Debug of Embedded Multi-Processor SoCs. In Proc. International Symposium on VLSI Design, Automation and Test, 2009.Google Scholar
  28. 28.
    Bart Vermeulen and Kees Goossens. Debugging Multi-Core Systems on Chip. In George Kornaros, editor, Multi-Core Embedded Systems, chapter 5, pages 153–198. CRC Press/Taylor & Francis Group, 2010.Google Scholar
  29. 29.
    Bart Vermeulen and Kees Goossens. Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks. In Proc. High-Level Design Validation and Test Workshop, 6 2010.Google Scholar
  30. 30.
    Bart Vermeulen and Kees Goossens. Interactive debugging of systems on chip with multiple clocks. IEEE Design and Test of Computers, 5 2011. Special issue on Transaction-Level Validation of Multicore Architectures.Google Scholar
  31. 31.
    B. Vermeulen, T. Waayers, and S.K. Goel. Core-based scan architecture for silicon debug. In Proc. IEEE International Test Conference, pages 638–647, 2002.Google Scholar
  32. 32.
    Bart Vermeulen, John Dielissen, Kees Goossens, and Cӑlin Ciordaş. Bringing Communication Networks On Chip: Test and Verification Implications. IEEE Communications Magazine, 41(9):74–81, 9 2003.Google Scholar
  33. 33.
    Bart Vermeulen, Zalfany Urfianto, and Sandeep Kumar Goel. Automatic Generation of Breakpoint Hardware for Silicon Debug. In Proc. Design Automation Conference, pages 514–517, San Diego, CA, USA, 6 2004.Google Scholar
  34. 34.
    Bart Vermeulen, Yu-Chin Hsu, and Robert Ruiz. Silicon Debug. Test and Measurement World Magazine, pages 41–45, 10 2006.Google Scholar
  35. 35.
    B. Vermeulen, K. Goossens, and S. Umrani. Debugging distributed-shared-memory communication at multiple granularities in networks on chip. In Proc. International Symposium on Networks on Chip, pages 3–12, 4 2008.Google Scholar
  36. 36.
    Wikipedia. Transistor count, 2012.Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  1. 1.NXP SemiconductorsEindhovenThe Netherlands
  2. 2.Faculty of Electrical EngineeringEindhoven University of TechnologyEindhovenThe Netherlands

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