Full-Search Free Intra Predication for H.264 Decoder

Abstract

The standard H.264/AVC Intra frame encoding process has several data dependent and computational intensive coding methodologies that limit the overall codec performance. It causes not only a high degree of computational complexity, but also an unacceptable delay especially for the real-time video applications. In Chap. 4, we have introduced an enhanced algorithm and its software solution for the Intra prediction in the H.264/AVC encoder side of the MPEG-2 to H.264/AVC transcoder. However, at some point, the information throughput capability of the software solution cannot keep up with the throughput requirement of real-time applications. Even with powerful high speed CPU’s, a backlog often occurs during the decoding process. In addition, when split-second situational awareness and decision making require the processing of huge volumes of information in real-time, the real benefit of the hardware solution shines. Moreover, the hardware-based solution introduces a far less parasitic drag than the software systems of the past. Clearly, the need for speed, which is inherited from the real-time demanding applications, necessitates the development of hardware solution for video codec standards. In this chapter of the book, a Low-power hardware architecture for the proposed high throughput Full-Search Free (FSF) Intra mode selection and direction prediction algorithm is proposed. In fact, the proposed Intra prediction hardware solution could be easily integrated in the H.264/AVC encoder side of the MPEG-2 to H.264/AVC transcoder, which has been discussed in Chap. 4. However, we realized that our design can perfectly work as an accelerating hardware solution for the stand alone standard H.264/AVC decoder devices. Accordingly, we focused on modifying the proposed FSF algorithm to fit into the standard H.264/AVC decoders. At first, we tested the modified version of the FSF algorithm after integrating it with the JM 18.2 reference software of the standard decoder. Then, we designed a power efficient hardware architecture for the proposed high throughput FSF algorithm. As a result, the introduced low-power/ high-throughput hardware implementation significantly reduces the computational complexity and the processing run-time that are required for the H.264/AVC Intra frame prediction process. As illustrated in Fig. 5.1, the FPGA prototyped version for the proposed architecture has achieved an operating frequency of 291 MHz at a power consumption of 112 mW when implemented on Virtex-5 FPGA development board. The FPGA simulation and testing that employed a standard video benchmark proved the efficiency and the functionality of the proposed Intra prediction architecture, specially for real-time H.264/AVC video codecs on mobile devices. Motivated by the FPGA experimental results, the ASIC implementation for the FSF architecture is carried out and synthesizing results are obtained. Our heavily tested 45 nm ASIC design was able to achieve an operating frequency of 140 MHz and limiting the overall power consumption to only 9.01 mW, which is strongly nominating our proposed Intra prediction hardware architecture for interactive real-time mobile video applications.