Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry
Prior to fabricating an integrated circuit, designers will often construct FPGA-based prototypes that can test and verify their circuits far more thoroughly than is possible within software simulations, such as by booting an operating system. A key limitation of physical prototypes, however, is the lack of on-chip observability necessary during debug. This paper describes a trace-buffer based platform that can be used to enhance FPGA observability. We use this platform to investigate how best to couple debug instruments with user circuitry, and how the subsequent debug loop — the process of changing the signals or trigger observed when converging on the root-cause of a bug — can be shortened. We demonstrate a working implementation of this platform on Xilinx technology, finding that runtime speedups for each debug loop of 1.2–3.0X (and potentially 5.7–11.2X) can be achieved on industrial benchmarks, when compared to re-instrumenting with vendor tools.
KeywordsVery Large Scale Integration Post Placement Post Synthesis Vendor Tool User Circuit
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