Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry

  • Eddie Hung
  • Jeffrey B. Goeders
  • Steven J. E. Wilton
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8405)


Prior to fabricating an integrated circuit, designers will often construct FPGA-based prototypes that can test and verify their circuits far more thoroughly than is possible within software simulations, such as by booting an operating system. A key limitation of physical prototypes, however, is the lack of on-chip observability necessary during debug. This paper describes a trace-buffer based platform that can be used to enhance FPGA observability. We use this platform to investigate how best to couple debug instruments with user circuitry, and how the subsequent debug loop — the process of changing the signals or trigger observed when converging on the root-cause of a bug — can be shortened. We demonstrate a working implementation of this platform on Xilinx technology, finding that runtime speedups for each debug loop of 1.2–3.0X (and potentially 5.7–11.2X) can be achieved on industrial benchmarks, when compared to re-instrumenting with vendor tools.


Very Large Scale Integration Post Placement Post Synthesis Vendor Tool User Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Sohanghpurwala, A.A., Athanas, P., Frangieh, T., Wood, A.: OpenPR: An Open-Source Partial-Reconfiguration Toolkit for Xilinx FPGAs. In: 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, Number Xdl, pp. 228–235. IEEE (May 2011)Google Scholar
  2. 2.
    Poulos, Z., Yang, Y.S., Anderson, J., Veneris, A., Le, B.: Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug. In: Proc. of the Conf. on Design, Automation Test in Europe, pp. 292–295 (March 2012)Google Scholar
  3. 3.
    Iskander, Y.S., Patterson, C.D., Craven, S.D.: Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug. In: Proc. of the 21st Int’l Conf. on Field Programmable Logic and Applications, pp. 518–523 (September 2011)Google Scholar
  4. 4.
    Hung, E., Wilton, S.J.E.: Scalable Signal Selection for Post-Silicon Debug. IEEE Trans. on Very Large Scale Integration (VLSI) Systems 21, 1103–1115 (2013)CrossRefGoogle Scholar
  5. 5.
    Hung, E., Wilton, S.J.E.: Incremental Trace-Buffer Insertion for FPGA Debug. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (accepted for publication April 2013)Google Scholar
  6. 6.
    Hung, E., Wilton, S.J.E.: Towards Simulator-like Observability for FPGAs: A Virtual Overlay Network for Trace-Buffers. In: Proc. of the 21st ACM/SIGDA Int’l Symp. on Field-Programmable Gate Arrays, pp. 19–28 (February 2013)Google Scholar
  7. 7.
    Rose, J., Luu, J., Yu, C.W., Densmore, O., Goeders, J., Somerville, A., Kent, K.B., Jamieson, P., Anderson, J.: The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing. In: Proc. of the 20th ACM/SIGDA Int’l Symp. on Field-Programmable Gate Arrays, pp. 77–86 (February 2012)Google Scholar
  8. 8.
    Hung, E., Jamal, A.-S., Wilton, S.J.E.: Maximum Flow Algorithms for Maximum Observability in FPGA Debug. In: Proc. of the 12th Int’l Conf. on Field-Programmable Technology (December 2013) (to appear)Google Scholar
  9. 9.
    Wheeler, T., Graham, P., Nelson, B.E., Hutchings, B.: Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. In: Proc. of the 11th Int’l Conf. on Field Programmable Logic and Applications, pp. 483–492 (August 2001)Google Scholar
  10. 10.
    Aeroflex Gaisler: GRLIB IP Core User’s Manual – v1.3.1 B4135 (August 2013),
  11. 11.
    Steiner, N., Wood, A., Shojaei, H., Couch, J., Athanas, P., French, M.: Torc: Towards an Open-Source Tool Flow. In: Proc. of the 19th ACM/SIGDA Int’l Symp. on Field-Programmable Gate Arrays, pp. 41–44 (February 2011)Google Scholar
  12. 12.
    Murray, K.E., Whitty, S., Liu, S., Luu, J., Betz, V.: Titan: Enabling large and complex benchmarks in academic CAD. In: Proc. of the 23rd Int’l Conf. on Field Programmable Logic and Applications, pp. 1–8 (September 2013)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Eddie Hung
    • 1
  • Jeffrey B. Goeders
    • 1
  • Steven J. E. Wilton
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of British ColumbiaVancouverCanada

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