Relocatable Hardware Threads in Run-Time Reconfigurable Systems

  • Alexander Wold
  • Andreas Agne
  • Jim Torresen
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8405)


Run-time reconfiguration provides an opportunity to increase performance, reduce cost and improve energy efficiency in FPGA-based systems. However, run-time reconfigurable systems are more complex to implement than static only systems. This increases time to market, and introduces run-time overhead into the system. Our research aims to raise the abstraction level to develop run-time reconfigurable systems. We present operating system extensions which enable seamless integration of run-time reconfigurable hardware threads into applications. To improve resource utilization, the hardware threads are placed on a fine granularity tile grid. We take advantage of a relocatable module placer targeting modern FPGA to manage the reconfigurable area. The module placer accurately models the FPGA resources to compute feasible placement locations for the hardware threads at run-time. Finally, we evaluate our work by means of a case study that consists of a synthetic application to validate the functionality and performance of the implementation. The results show a reduction in reconfiguration time of up to 42% and more than double resource utilization.


Application Programming Interface Very Large Scale Integration Module Placer FPGA Resource Improve Resource Utilization 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Sohanghpurwala, A.A., Athanas, P., Frangieh, T., Wood, A.: OpenPR: An Open-Source Partial-Reconfiguration Toolkit for Xilinx FPGAs. In: 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, Number Xdl, pp. 228–235. IEEE (May 2011)Google Scholar
  2. 2.
    Beckhoff, C., Koch, D., Torresen, J.: Go Ahead: A Partial Reconfiguration Framework. In: 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, pp. 37–44. IEEE (April 2012)Google Scholar
  3. 3.
    Jara-Berrocal, A., Gordon-Ross, A.: An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips. In: ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, pp. 219–222. IEEE (September 2011)Google Scholar
  4. 4.
    Wang, Y., Zhou, X., Wang, L., Yan, J., Luk, W.: SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (99), 1–14 (2013)Google Scholar
  5. 5.
    Lubbers, E., Platzner, M.: ReconOS: An RTOS Supporting Hard-and Software Threads. In: 2007 International Conference on Field Programmable Logic and Applications, pp. 441–446. IEEE (August 2007)Google Scholar
  6. 6.
    Wold, A., Koch, D., Torresen, J.: Enhancing Resource Utilization with Design Alternatives in Runtime Reconfigurable Systems. In: 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, Anchorage, pp. 264–270. IEEE (May 2011)Google Scholar
  7. 7.
    Koester, M., Luk, W., Hagemeyer, J., Porrmann, M., Ruckert, U.: Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19(6), 1048–1061 (2011)CrossRefGoogle Scholar
  8. 8.
    Koch, D., Beckhoff, C., Torresen, J.: Zero logic overhead integration of partially reconfigurable modules. In: Proceedings of the 23rd Symposium on Integrated Circuits and System Design - SBCCI 2010, p. 103. ACM Press, New York (2010)Google Scholar
  9. 9.
    COSRECOS: Context switching reconfigurable hardware for communication systems (cosrecos),
  10. 10.
    EPiCS: Engineering proprioception in computing systems (epics),

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Alexander Wold
    • 1
  • Andreas Agne
    • 2
  • Jim Torresen
    • 1
  1. 1.Department of InformaticsUniversity of OsloNorway
  2. 2.Computer Engineering DepartmentUniversity of PaderbornGermany

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