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Instruction Extension and Generation for Adaptive Processors

  • Chao Wang
  • Xi Li
  • Huizhen Zhang
  • Liang Shi
  • Xuehai Zhou
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8405)

Abstract

Adaptive reconfigurable instruction-set processors (RISP) is an emerging research field for state-of-the-art VLIW processors. However, it still poses significant challenges to generate and map the original codes to the custom instructions. In this paper we propose an architecture framework to extend new instructions for adaptive RISP. The selected hotspot is considered as a custom instruction and implemented in reconfigurable hardware units. An instruction generator is used to provide a mapping mechanism from hot blocks to hardware implementations, using data flow analysis, instruction clustering, subgraph enumerating and subgraph merging techniques. To demonstrate the effectiveness and performance of the framework and to verify the correctness of the mapping mechanism, a prototype instruction generator has been implemented.

Keywords

Instructions Extension Adaptive Multicore Processors 

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References

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Chao Wang
    • 1
  • Xi Li
    • 1
  • Huizhen Zhang
    • 2
  • Liang Shi
    • 3
  • Xuehai Zhou
    • 1
  1. 1.School of Computer ScienceUniversity of Science and Technology of ChinaChina
  2. 2.School of Computer ScienceHuaqiao UniversityChina
  3. 3.School of Computer ScienceChongqing UniversityChina

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